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| stm8s105xx access line, 16 mhz stm8s 8 - bit mcu, up to 32 kbytes flash, integrated eeprom,10 - bit adc, timers, uart, spi, i2c datasheet - production data features core ? 16 mhz advanced stm8 core with harvard architecture and 3 - stage pipeline ? extended instruction set memories ? medium - density flash/eeprom: ? program memory up to 32 kbytes; data retention 20 years at 55c after 10 kcycles ? data memory up to 1 kbytes true data eepr om; endurance 300 kcycles ? ram: up to 2 kbytes clock, reset and supply management ? 2.95 v to 5.5 v operating voltage ? flexible clock control, 4 master clock sources: ? low power crystal resonator oscillator ? external clock input ? internal, user - trimmable 1 6 mhz rc ? internal low power 128 khz rc ? clock security system with clock monitor ? power management: ? low power modes (wait, active - halt, halt) ? switch - off peripheral clocks individually ? permanently active, low consumption power -on and power - down reset i nterrupt management ? nested interrupt controller with 32 interrupts ? up to 37 external interrupts on 6 vectors timers ? 2x 16 - bit general purpose timers, with 2+3 capcom channels (ic, oc or pwm) ? advanced control timer: 16 - bit, 4 capcom channels, 3 compleme ntary outputs, dead - time insertion and flexible synchronization ? 8 - bit basic timer with 8- bit prescaler ? auto wake - up timer ? window and independent watchdog timers communications interfaces ? uart with clock output for synchronous operation, smartcard, irda , lin ? spi interface up to 8 mbit/s ? i 2 c interface up to 400 kbit/s analog - to - digital converter (adc) ? 10- bit, 1 lsb adc with up to 10 multiplexed channels, scan mode and analog watchdog i/os ? up to 38 i/os on a 48 - pin package including 16 high sink out puts ? highly robust i/o design, immune against current injection development support ? embedded single wire interface module (swim) for fast on - chip programming and non- intrusive debugging unique id ? 96- bit unique key for each device table 1: device su mmary reference part number stm8s105xx stm8s105k4, stm8 s105k6, stm8s105s4, stm8s105s6, stm8s105c4 , stm8s105c6 february 2014 docid14771 rev 13 1 / 99 this is information on a product in full production www.st.com
contents stm8s105xx contents 1 introduction ....................................................................................... 8 2 description ........................................................................................ 9 3 block diagram ................................................................................. 10 4 product overview ............................................................................ 11 4.1 single wire interface module (swim) and debug module (dm) ....... 11 4.2 interrupt controller ........................................................................... 12 4.3 flash program and data eeprom memory .................................... 12 4.4 clock controller ............................................................................... 13 4.5 power management ........................................................................ 14 4.6 watchdog timers ............................................................................. 14 4.7 auto wakeup counter ...................................................................... 15 4.8 beeper ............................................................................................ 15 4.9 tim1 - 16- bit advanced control timer ............................................... 15 4.10 tim2, tim3 - 16- bit general purpose timers .................................... 15 4.11 tim4 - 8 - bit basi c timer ................................................................... 16 4.12 analog - to - digital converter (adc1) ................................................. 16 4.13 communication interfaces ............................................................... 17 4.13.1 uart2 ................................ ................................ .............................. 17 4.13.2 spi ................................ ................................ ................................ .... 17 4.13.3 i2c ................................ ................................ ................................ ..... 18 5 pinout and pin description ............................................................ 19 5.1 stm8s105 pinouts and pin description ........................................... 19 5.1.1 alternate function remapping ................................ ........................... 24 6 memory and register map .............................................................. 25 6.1 memory map ................................................................................... 25 6.2 register map ................................................................................... 26 6.2.1 i/o port hardware register map ................................ ........................ 26 6.2.2 general hardware register map ................................ ........................ 27 6.2.3 cpu/swim/debug module/interrupt controller registers .................. 34 7 interrupt vector mapping ............................................................... 36 8 option bytes .................................................................................... 37 9 unique id ......................................................................................... 41 2 / 99 docid14771 rev 13 stm8s105xx contents 10 electrical characteristics ............................................................... 42 10.1 parameter conditions ...................................................................... 42 10.1.1 minimum and maximum values ................................ ........................ 42 10.1.2 typical values ................................ ................................ ................... 42 10.1.3 typical curves ................................ ................................ ................... 42 10.1.4 typical current consumption ................................ ............................ 42 10.1.5 loading capacitor ................................ ................................ ............. 43 10.1.6 pin input voltage ................................ ................................ ............... 43 10.2 absolute maximum ratings .............................................................. 43 10.3 operating conditions ....................................................................... 45 10.3.1 vcap external capacitor ................................ ................................ .. 46 10.3.2 supply current characteristics ................................ .......................... 47 10.3.3 external clock sources and timing characteristics ............................ 56 10.3.4 internal clock sources and timing characteristics ............................. 58 10.3.5 m emory characteristics ................................ ................................ ..... 60 10.3.6 i/o port pin characteristics ................................ ................................ 61 10.3.7 typical output level curves ................................ ............................... 64 10.3.8 reset pin characteristics ................................ ................................ .. 68 10.3.9 spi serial peripheral interface ................................ .......................... 70 10.3.10 i2c interface characteristics ................................ ............................. 73 10.3.11 10- bit adc characteristics ................................ ................................ 74 10.3.12 emc characteristics ................................ ................................ .......... 77 11 package information ...................................................................... 80 11.1 48- pin lqfp package mechanical data .......................................... 80 11.2 44- pin lqfp package mechanical data .......................................... 81 11.3 32- pin lqfp package mechanical data .......................................... 82 11.4 32- lead ufqfpn package mechanical data ................................... 84 11.5 sdip32 package mechanical data .................................................. 85 12 thermal characteristics ................................................................. 87 12.1 referen ce document ....................................................................... 87 12.2 selecting the product temperature range ........................................ 87 13 ordering information ...................................................................... 89 14 stm8s105 fastrom microcontroller option list ....................... 90 15 stm8 development tools ............................................................... 94 15.1 emulation and in - circuit debugging tools ......................................... 94 docid14771 rev 13 3 / 99 contents stm8s105xx 15.2 software tools ................................................................................. 94 15.2.1 stm8 toolset ................................ ................................ .................... 94 15.2.2 c and assembly toolchains ................................ .............................. 95 15.3 programming tools .......................................................................... 95 16 revision history .............................................................................. 96 17 disclaimer ....................................................................................... 99 4 / 99 docid14771 rev 13 stm8s105xx list of tables list of tables table 1: device summary ................................ ................................ ................................ ........................... 1 t able 2: stm8s105xx access line features ................................ ................................ ............................... 9 table 3: peripheral clock gating bit assignments in clk_pckenr1/2 registers ................................ .... 14 table 4 : tim timer features ................................ ................................ ................................ ....................... 16 table 5: legend/abbreviations for pinout tables ................................ ................................ ....................... 19 table 6: pin description for stm8s105 microcontroller s ................................ ................................ ......... 22 table 7: flash, data eeprom and ram boundary addresses ................................ ............................... 26 table 8: i/o port hardware register map ................................ ................................ ................................ ... 26 table 9: general hardware register map ................................ ................................ ................................ .. 27 table 10: cpu/swim/debug module/interrupt controller registers ................................ .......................... 34 table 11: interrupt mapping ................................ ................................ ................................ ...................... 36 table 12: option bytes ................................ ................................ ................................ .............................. 37 table 13: option byte description ................................ ................................ ................................ ............. 38 table 14: description of alternate function remapping bits [7:0] of opt2 ................................ ................ 39 table 15: unique id registers (96 bits) ................................ ................................ ................................ ..... 41 table 16: voltage characteristics ................................ ................................ ................................ .............. 43 table 17: current characteristics ................................ ................................ ................................ .............. 44 table 18: t hermal characteristics ................................ ................................ ................................ ............. 45 table 19: general operating conditions ................................ ................................ ................................ .... 45 table 20: operating conditions at power - up/power - down ................................ ................................ ........ 46 table 21: total current consumption with code execution in run mode at vdd = 5 v ............................. 47 table 22: total current consumption with code e xecution in run mode at vdd = 3.3 v .......................... 48 table 23: total current consumption in wait mode at vdd = 5 v ................................ ............................. 49 table 24: total current consumption in wait mode at vdd = 3.3 v ................................ .......................... 49 table 25: total current consumption in active halt mode at vdd = 5 v ................................ ................... 50 table 26: tot al current consumption in active halt mode at vdd = 3.3 v ................................ ................ 51 table 27: total current consumption in halt mode at vdd = 5 v ................................ ............................. 51 ta ble 28: total current consumption in halt mode at vdd = 3.3 v ................................ .......................... 52 table 29: wakeup times ................................ ................................ ................................ ........................... 52 table 30: total current consumption a nd timing in forced reset state ................................ ...................... 53 table 31: peripheral current consumption ................................ ................................ ................................ 53 table 32: hse user external clock characteristics ................................ ................................ ................... 56 table 33: hse oscillator characteristics ................................ ................................ ................................ ... 56 table 34: hsi oscillator characteristics ................................ ................................ ................................ ..... 58 table 35: lsi oscillator characteristics ................................ ................................ ................................ ..... 59 table 36: ram and hardware registers ................................ ................................ ................................ .... 60 table 37: flash program memory/data eeprom memory ................................ ................................ ...... 60 table 38: i/o static characteristics ................................ ................................ ................................ ............ 61 table 39: output driving current (standard ports) ................................ ................................ ..................... 63 table 40: output driving current (true open drain ports) ................................ ................................ .......... 63 table 41: output driving current (high sink ports) ................................ ................................ .................... 63 table 42: nrst pin characteristics ................................ ................................ ................................ .......... 68 table 43: spi characteristics ................................ ................................ ................................ .................... 71 table 44: i2c characteristics ................................ ................................ ................................ .................... 73 table 45: adc characteristics ................................ ................................ ................................ .................. 74 table 46: adc accuracy with rain < 10 k , vdda= 5 v ................................ ................................ ...... 75 table 47: adc accuracy with rain < 10 k rain, vdda = 3.3 v ................................ .......................... 76 table 48: ems data ................................ ................................ ................................ ................................ .. 78 table 49: emi data ................................ ................................ ................................ ................................ .... 78 table 50: esd absolute maximum ratings ................................ ................................ ............................... 79 table 51: electrical sensitivities ................................ ................................ ................................ ................ 79 table 52: 48 - pin low profile quad flat package mechanical data ................................ .............................. 80 table 53: 44 - pin low profile quad flat package mechanical data ................................ .............................. 81 docid14771 rev 13 5 / 99 list of tables stm8s105xx table 54: 32 - pin low profile quad flat package mechanical data ................................ .............................. 82 table 55: 32 - lead ultra thin fine pitch quad flat no - lead package mechanic al data ................................ . 84 table 56: 32 - lead shrink plastic dip (400 ml) package mechanical data ................................ ................. 86 table 57: thermal characteristics (1) ................................ ................................ ................................ ....... 87 table 58: document revision history ................................ ................................ ................................ ........ 96 6 / 99 docid14771 rev 13 stm8s105xx list of figures list of figures figure 1: stm8s105xx access line block diagram ................................ ................................ ................... 10 figure 2: flash memory organization ................................ ................................ ................................ ....... 13 figure 3: lqfp 48 - pin pinout ................................ ................................ ................................ ................... 19 figure 4: lqfp 44 - pin pinout ................................ ................................ ................................ ................... 20 figure 5: lqfp/ufqfpn 32 - pin pinout ................................ ................................ ................................ .... 21 figure 6: sdip 32 - pin pinout ................................ ................................ ................................ .................... 21 figure 7: memory map ................................ ................................ ................................ .............................. 25 figure 8: supply current measurement conditions ................................ ................................ ................... 42 fig ure 9: pin loading conditions ................................ ................................ ................................ ................ 43 figure 10: pin input voltage ................................ ................................ ................................ ...................... 43 figure 11: fcpumax versus vdd ................................ ................................ ................................ ............. 46 figure 12: external capacitor cext ................................ ................................ ................................ ......... 47 figure 13: typ. idd(run) vs. vdd, hse user external clock, fcpu = 16 mhz ................................ ...... 54 figure 14: typ. idd(run) vs. fcpu, hse user external clock, vdd= 5 v ................................ .............. 54 figure 15: typ. idd(run) vs. vdd, hsi rc osc, fcpu = 16 mhz ................................ .......................... 54 figure 16: typ. idd(wfi) vs. vdd, hse user external clock, fcpu = 16 mhz ................................ ....... 55 figure 17: typ. idd(wfi) vs. fcpu, hse user external clock vdd = 5 v ................................ ............... 55 figure 18: typ. idd(wfi) vs. vdd, hsi rc osc, fcpu = 16 mhz ................................ ........................... 55 figure 19: hse external clocksource ................................ ................................ ................................ ....... 56 figure 20: hse oscillator circuit diagram ................................ ................................ ................................ .. 57 figure 21: typical hsi accuracy at vdd = 5 v vs 5 temperatures ................................ ........................... 58 figure 22: typical hsi accuracy vs vdd @ 4 temperatures ................................ ................................ ... 59 figure 23: typical lsi accuracy vs vdd @ 4 temperatures ................................ ................................ .... 59 figure 24: typical vil and vih vs vdd @ 4 temperatures ................................ ................................ ..... 62 figure 25: typical pull - up resistance vs vdd @ 4 temperatures ................................ ............................. 62 figure 26: typical pull - up current vs vdd @ 4 temperatures ................................ ................................ .. 63 figure 27: typ. vol @ vdd = 5 v (standard ports) ................................ ................................ ................ 64 figure 28: typ. vol @ vdd = 3.3 v (standard ports) ................................ ................................ ............. 65 figure 29: typ. vol @ vdd = 5 v (true open drain ports) ................................ ................................ ...... 65 figure 30: typ. vol @ vdd = 3.3 v (true open drain ports) ................................ ................................ ... 66 figure 31: typ. vol @ vdd = 5 v (high sink ports) ................................ ................................ ................ 66 figure 32: typ. vol @ vdd = 3.3 v (high sink ports) ................................ ................................ ............. 67 figure 33: typ. vdd - voh @ vdd = 5 v (standard ports) ................................ ................................ ..... 67 figure 34: typ. vdd - voh @ vdd = 3.3 v (standard ports) ................................ ................................ .. 67 figure 35: typ. vdd - voh @ vdd = 5 v (high sink ports) ................................ ................................ .... 68 figure 36: typ. vdd - voh @ vdd = 3.3 v (high sink ports) ................................ ................................ . 68 figure 37: typical nrst vil and vih vs vdd @ 4 temperatures ................................ ........................... 69 figure 38: typical nrst pull - up resistance vs vdd @ 4 temperatures ................................ .................. 69 figure 39: typical nrst pull - up current vs vdd @ 4 temperatures ................................ ....................... 70 figure 40: recommended reset pin protection ................................ ................................ ........................ 70 figure 41: spi timing diagram - slave mode and cpha = 0 ................................ ................................ .... 72 figure 42: spi timing diagram - slave mode and cpha = 1(1) ................................ ................................ 72 figure 43: spi timing diagram - master mode(1) ................................ ................................ ..................... 73 figure 44: typical application with i2c bus and timing diagram (1) ................................ ......................... 74 figure 45: adc accuracy characteristics ................................ ................................ ................................ .. 76 figure 46: typical application with adc ................................ ................................ ................................ ... 77 figure 47: 48 - pin l ow profile quad flat package (7 x 7) ................................ ................................ ............. 80 figure 48: 44 - pin low profile quad flat package ................................ ................................ ........................ 81 figure 49: 32 - pin low profile quad fl at package (7 x 7) ................................ ................................ ............. 82 figure 50: 32 - lead, ultra thin, fine pitch quad flat no - lead package (5 x 5) ................................ .............. 84 figure 51: 32 - lead shrink plastic dip (400 ml) package ................................ ................................ ........... 85 figure 52: stm8s105xx access line ordering information scheme ................................ ......................... 89 docid14771 rev 13 7 / 99 introduction st m8s105xx 1 introduction this dat asheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information. ? for complete information on the stm8s microcontroller memory, registers and peripherals, please refer to the stm8s microc ontroller family reference manual (rm0016). ? for information on programming, erasing and protection of the internal flash memory please refer to the stm8s flash programming manual (pm0051). ? for information on the debug and swim (single wire interface modu le) refer to the stm8 swim communication protocol and debug module user manual (um0470). ? for information on the stm8 core, please refer to the stm8 cpu programming manual (pm0044). 8 / 99 docid14771 rev 13 stm8s105xx description 2 description the stm8s105xx access l ine 8 - bit microcontrollers offer from 16 to 32 kbytes flash program memory, plus integrated true data eeprom. they are referred to as medium - density devices in the stm8s microcontroller family reference manual (rm0016). all devices of the stm8s105xx acces s line provide the following benefits: reduced system cost, performance and robustness, short development cycles, and product longevity. the system cost is reduced thanks to an integrated true data eeprom for up to 300k write/erase cycles and a high syste m integration level with internal clock oscillators, watchdog, and brown - out reset. device performance is ensured by a 16 mhz cpu clock frequency and enhanced characteristics which include robust i/o, independent watchdogs (with a separate clock source), and a clock security system. short development cycles are guaranteed due to application scalability across common family product architecture with compatible pinout, memory map and modular peripherals. full documentation is offered with a wide choice of d evelopment tools. product longevity is ensured in the stm8s family thanks to their advanced core which is made in a state - of - the art technology for applications with 2.95 v to 5.5 v operating supply. table 2: stm8s105xx access line features device stm8s 105c6 stm8s105c4 stm8s105s6 stm8s105s4 stm8s105k6 stm8s105k4 pin count 48 48 44 44 32 32 maximum number of gpios 38 38 34 34 25 25 ext. interrupt pins 35 35 31 31 23 23 timer capcom channels 9 9 8 8 8 8 timer compleme ntary outputs 3 3 3 3 3 3 a/d converter channels 10 10 9 9 7 7 high sink i/os 16 16 15 15 12 12 medium density flash program memory (bytes) 32k 16k 32k 16k 32k 16k data eeprom (bytes) 1024 1024 1024 1024 1024 1024 ra m (bytes) 2k 2k 2k 2k 2k 2k peripheral set advanced control timer (tim1), general - purpose timers (tim2 and tim3), basic timer (tim4) spi, i 2 c, uart, window wdg, independent wdg, adc docid14771 rev 13 9 / 99 block diagram st m8s105xx 3 block diagram figure 1 : stm8s105xx a ccess line block diagram 10/ 99 docid14771 rev 13 stm8s105xx product overview 4 product overview the following section intends to give an overview of the basic features of the device functional modules and peripherals. for more detailed information please refer to the corresponding family reference manual (rm0016). central processing unit stm8 the 8 - bit stm8 core is designed for code efficiency and performance. it contains 6 internal registers which are direct ly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions. architecture and registers ? harvard architecture ? 3 - stage pipeline ? 32- bit wide program memory bus - single cycle fetching for most instructions ? x and y 16 - bit index registers - enabling indexed addressing modes with or without offset and read - modify - write type data manipulations ? 8 - bit accumulator ? 24- bit program counter - 16 - mbyte linear memory space ? 16- bit stack pointer - access to a 64 k - level stack ? 8 - bit condition code register - 7 condition flags for the result of the last instruction addressing ? 20 addressing modes ? indexed indirect addressing mode for look - up tables located anywhere in the address space ? stack point er relative addressing mode for local variables and parameter passing instruction set ? 80 instructions with 2 - byte average instruction size ? standard data movement and logic/arithmetic functions ? 8 - bit by 8 - bit multiplication ? 16- bit by 8 - bit and 16 - bit by 16- bit division ? bit manipulation ? data transfer between stack and accumulator (push/pop) with direct stack access ? data transfer using the x and y registers or direct memory - to - memory transfers 4.1 single wire interface module (swim) and debug module (dm) the single wire interface module and debug module permits non - intrusive, real - time in - circuit debugging and fast memory programming. swim single wire interface module for direct access to the debug module and memory programming. the interface can be activated in all device operation modes. the maximum data transmission speed is 145 bytes/ms. docid14771 rev 13 11/ 99 pr oduct overview st m8s105xx debug module the non - intrusive debugging module features a performance close to a full - featured emu lator. beside memory and peripherals, also cpu operation can be monitored in real - time by means of shadow registers. ? r/w to ram and peripheral registers in real - time ? r/w access to all resources by stalling the cpu ? breakpoints on all program - memory instr uctions (software breakpoints) ? two advanced breakpoints, 23 predefined configurations 4.2 interrupt controller ? nested interrupts with three software priority levels ? 32 interrupt vectors with hardware priority ? up to 37 external interrupts on 6 vectors including tli ? trap and reset interrupts 4.3 flash program and data eeprom memory ? up to 32 kbytes of flash program single voltage flash memory ? up to 1 kbytes true data eeprom ? read while write: writing in data memory possible while executing code in program memory ? user option byte area write protection (wp) write protection of flash program memory and data eeprom is provided to avoid unintentional overwriti ng of memory that could result from a user software malfunction. there are two levels of write protection. the first level is known as mass (memory access security system). mass is always enabled and protects the main flash program memory, data eeprom and option bytes. to perform in - application programming (iap), this write protection can be removed by writing a mass key sequence in a control register. this allows the application to write to data eeprom, modify the contents of main program memory or the d evice option bytes. a second level of write protection, can be enabled to further protect a specific area of memory known as ubc (user boot code). refer to the figure below. the size of the ubc is programmable through the ubc option byte, in increments o f 1 page (512 bytes) by programming the ubc option byte in icp mode. this divides the program memory into two areas: ? main program memory: up to 32 kbytes minus ubc ? user - specific boot code (ubc): configurable up to 32 kbytes the ubc area remains write - p rotected during in - application programming. this means that the mass keys do not unlock the ubc area. it protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the iap and com munication routines. 12/ 99 docid14771 rev 13 stm8s105xx product overview figure 2 : flash memory organization read - out protection (rop) the read - out protection blocks reading and writing the flash program memory and data eeprom memory in icp mode (and debug mode). once the read - ou t protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose m icrocontroller. 4.4 clock controller the clock controller distributes the system clock (f master ) coming from different oscillators to the core and the peripherals. it also manages clock gating for low power modes and ensures clock robustness. features ? clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler. ? safe clock switching: clock sources can be c hanged safely on the fly in run mode through a configuration register. the clock signal is not switched until the new clock source is ready. the design guarantees glitch - free switching. ? clock management: to reduce power consumption, the clock controller c an stop the clock to the core, individual peripherals or memory. ? master clock sources: four different clock sources can be used to drive the master clock: ? 1 - 16 mhz high - speed external crystal (hse) ? up to 16 mhz high - speed user - external clock (hse user - e xt) ? 16 mhz high - speed internal rc oscillator (hsi) ? 128 khz low - speed internal rc (lsi) docid14771 rev 13 13/ 99 product overview st m8s105xx ? startup clock: after reset, the microcontroller restarts by default with an internal 2 mhz clock (hsi/8). the prescaler ratio and clock source can be changed by the a pplication program as soon as the code execution starts. ? clock security system (css): this feature can be enabled by software. if an hse clock failure occurs, the internal rc (16 mhz/8) is automatically selected by the css and an interrupt can optionally be generated. ? configurable main clock output (cco): this outputs an external clock for use by the application. table 3: peripheral clock gating bit assignments in clk_pckenr1/2 registers bit peripheral clock bit peripheral clock bit peripheral clock bit peripheral clock pcken17 tim1 pcken13 uart2 pcken27 reserved pcken23 adc pcken16 tim3 pcken12 reserved pcken26 reserved pcken22 awu pcken15 tim2 pcken11 spi pcken25 reserved pcken21 reserved pcken14 tim4 pcken10 i 2 c pcken24 reserved pcken20 reserved 4.5 power management for efficient power management, the application can be put in one of four different low - power modes. you can configure each mode to obtain the best compromi se between lowest power consumption, fastest start - up time and available wakeup sources. ? wait mode: in this mode, the cpu is stopped, but peripherals are kept running. the wakeup is performed by an internal or external interrupt or reset. ? active halt mod e with regulator on: in this mode, the cpu and peripheral clocks are stopped. an internal wakeup is generated at programmable intervals by the auto wake up unit (awu). the main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. wakeup is triggered by the internal awu interrupt, external interrupt or reset. ? active halt mode with regulator off: this mode is the same as active halt with regulator on, except that th e main voltage regulator is powered off, so the wake up time is slower. ? halt mode : in this mode the microcontroller uses the least power. the cpu and peripheral clocks are stopped, the main voltage regulator is powered off. wakeup is triggered by external event or reset. 4.6 watchdog timers the watchdog system is based on two independent timers providing maximum security to the applications. activation of the watchdog timers is controlled by option bytes or by softwa re. once activated, the watchdogs cannot be disabled by the user program without performing a reset. window watchdog timer the window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpect ed logical conditions, which cause the application program to abandon its normal sequence. the window function can be used to trim the watchdog behavior to match the application perfectly. 14/ 99 docid14771 rev 13 stm8s105xx product overview the application software must refresh the counter before time - out and during a limited time window. a reset is generated in two situations: 1. timeout: at 16 mhz cpu clock the time - out period can be adjusted between 75 s up to 64 ms. 2. refresh out of window: the downcounter is refreshed before its value is lower than the one stored in the window register. independent watchdog timer the independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. it is clocked by the 128 khz lsi internal rc clock source, and thus sta ys active even in case of a cpu clock failure the iwdg time base spans from 60 s to 1 s. 4.7 auto wakeup counter ? used for auto wakeup from active halt mode ? clock source: internal 128 khz internal low frequency rc oscillator or external clock ? lsi clock can be internally connected to tim3 input capture channel 1 for calibration 4.8 beeper the beeper function outputs a signal on the beep pin for sound generation. the signal is in the range of 1, 2 or 4 khz. the beeper output port is only available through the alternate function remap option bit afr7. 4.9 tim1 - 16 - bit advanced control timer this is a high - end timer designed for a wide range of control applications. with its complementary outputs, dead - time control and center - aligned pwm capability, the field of applications is extended to motor control, lighting and half - bridge driver ? 16- bit up, down and up/down autoreload coun ter with 16 - bit prescaler ? four independent capture/compare channels (capcom) configurable as input capture, output compare, pwm generation (edge and center aligned mode) and single pulse mode output ? synchronization module to control the timer with extern al signals ? break input to force the timer outputs into a defined state ? three complementary outputs with adjustable dead time ? encoder mode ? interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break 4.10 tim2, tim3 - 16- bit general p urpose timers ? 16- bit autoreload (ar) up - counter ? 15- bit prescaler adjustable to fixed power of 2 ratios 1?32768 ? timers with 3 or 2 individually configurable capture/compare channels ? pwm mod e ? interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update docid14771 rev 13 15/ 99 product overview st m8s105xx 4.11 tim4 - 8 - bit basic timer ? 8 - bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 ? clock source: cpu cloc k ? interrupt source: 1 x overflow/update table 4: tim timer features timer counter size (bits) prescaler counting mode capcom channels complem. outputs ext. trigger timer synchronization/ chaining tim1 16 any integer from 1 to 65536 up/down 4 3 yes no tim2 16 any power of 2 from 1 to 32768 up 3 0 no tim3 16 any power of 2 from 1 to 32768 up 2 0 no tim4 8 any power of 2 from 1 to 128 up 0 0 no 4.12 analog - to - digital converter (adc1) the stm8s105xx products contain a 10 - bit successive approximation a/d converter (adc1) with up to 10 multiplexed input channels and the following main features: ? input voltage range: 0 to v dd ? input voltage range: 0 to v dda ? conversi on time: 14 clock cycles ? single and continuous and buffered continuous conversion modes ? buffer size (n x 10 bits) where n = number of input channels ? scan mode for single and continuous conversion of a sequence of channels ? analog watchdog capability wit h programmable upper and lower thresholds ? analog watchdog interrupt ? external trigger input ? trigger from tim1 trgo ? end of conversion (eoc) interrupt additional ain12 analog input is not selectable in adc scan mode or with analog watchdog. values con verted from ain12 are stored only into the adc_drh/adc_drl registers. 16/ 99 docid14771 rev 13 stm8s105xx product overview 4.13 communication interfaces the following communication interfaces are implemented: ? uart2: full feature uart, synchronous mode, spi master mode, smartcard mode, irda mode, lin2.1 master/slave capability ? spi : full and half - duplex, 8 mbit/s ? i2c: up to 400 kbit/s 4.13.1 uart2 main features ? one mbit/s full duplex sci ? spi emulation ? high precision baud rate g enerator ? smartcard emulation ? irda sir encoder decoder ? lin master mode ? lin slave mode asynchronous communication (uart mode) ? full duplex communication - nrz standard format (mark/space) ? programmable transmit and receive baud rates up to 1 mbit/s (f cpu /16) and capable of following any standard baud rate regardless of the input frequency ? separate enable bits for transmitter and receiver ? two receiver wakeup modes: ? address bit (msb) ? idle line (interrupt) ? transmission error detection with interrupt gen eration ? parity control synchronous communication ? full duplex synchronous transfers ? spi master operation ? 8 - bit data communication ? maximum speed: 1 mbit/s at 16 mhz (f cpu /16) lin master mode ? emission: generates 13 - bit synch break frame ? reception: dete cts 11 - bit break frame lin slave mode ? autonomous header handling - one single interrupt per valid message header ? automatic baud rate synchronization - maximum tolerated initial clock deviation 15 % ? synch delimiter checking ? 11- bit lin synch break detec tion - break detection always active ? parity check on the lin identifier field ? lin error management ? hot plugging support 4.13.2 spi ? maximum speed: 8 mbit/s (f master /2) both for master and slave ? full duplex synchronous transfers docid14771 rev 13 17/ 99 product overview st m8s105xx ? simplex synchronous transfers on two lines with a possible bidirectional data line ? master or slave operation - selectable by hardware or software ? crc calculation ? 1 byte tx and rx buffer ? slave/master selection input pin 4.13.3 i2c ? i2c master features: ? clock generation ? start and stop generation ? i2c slave features: ? programmable i2c address detection ? stop bit detection ? generation and detection of 7 - bit/10 - bit addressing and general call ? supports different communication speeds: ? standard speed (up to 100 khz) ? fast speed (up to 400 khz) 18/ 99 docid14771 rev 13 stm8s105xx pinout and pin description 5 pinout and pin description table 5: legend/abbreviations for pinout tables type i= input, o = output, s = power supply level input cm = cmos output hs = high sink output speed o1 = slow (up to 2 mhz) o2 = fast (up to 10 mhz) o3 = fast/slow programmability with slow as default state after reset o4 = fast/slow programmability with fast as default state after reset port and cont rol configuration input float = floating, wpu = weak pull - up output t = true open drain, od = open drain, pp = push pull reset state bold x (pin state after internal reset release). unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release. 5.1 stm8s105 pinouts and pin description figure 3 : lqfp 48 - pin pinout 1. (hs) high sink capability. 2. (t) true open drain (p - buffer and protection diode to v dd not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). docid14771 rev 13 19/ 99 pinout and pin description st m8s105xx figure 4 : lqfp 44 - pin pinout 1. (hs) high sink capability. 2. (t) true open drain (p - buffer and protection diode to v dd not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a d uplication of the function). 20/ 99 docid14771 rev 13 stm8s105xx pinout and pin description figure 5 : lqfp/ufqfpn 32 - pin pinout 1. (hs) high sink capability. 2. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplica tion of the function). figure 6 : sdip 32 - pin pinout 1. (hs) high sink capability. 2. (t) true open drain (p - buffer and protection diode to v dd not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). docid14771 rev 13 21/ 99 pinout and pin description st m8s105xx table 6: pin description for stm8s105 microcontrollers pin number pin name type input output main function (after reset) default alternate function alternate func tion after remap [option bit] lqfp48 lqfp44 lqfp32/ ufqfpn32 sdip32 floating wpu ext. interrupt high sink speed od pp 1 1 1 6 nrst i/o x reset 2 2 2 7 pa1/ osc in i/o x x o1 x x port a1 resonator crystal in 3 3 3 8 pa2/ osc out i/o x x x o1 x x port a2 resonator crystal out 4 4 - - v ssio_1 s i/o ground 5 5 4 9 v ss s digital ground 6 6 5 10 vcap s 1.8 v regulator capacitor 7 7 6 11 v dd s digital power supply 8 8 7 12 v ddio_1 s i/o power supply 9 - - - pa3/ tim2 _ch3 [tim3 _ch1] i/o x x x o1 x x port a3 timer 2 - channel 3 tim3_ ch1 [afr1] 10 9 - - pa4 i/o x x x hs o3 x x port a4 11 10 - - pa5 i/o x x x hs o3 x x port a5 12 11 - - pa6 i/o x x x hs o3 x x port a6 - - 8 13 pf4/ ain12 (1) i/o x x o1 x x port f4 analog input 12 (2) 13 12 9 14 v dda s analog power supply 14 13 10 15 v ssa s analog ground 15 14 - - pb7/ ain7 i/o x x x o1 x x port b7 analog input 7 16 15 - - pb6/ ain6 i/o x x x o1 x x port b6 analog input 6 17 16 11 16 pb5/ ain5 [i 2 c _ sda] i/o x x x o1 x x port b5 analog input 5 i 2 c_sda [afr6] 18 17 12 17 pb4/ ain4 [i 2 c_ scl] i/o x x x o1 x x port b4 analog input 4 i 2 c_scl [afr6] 19 18 13 18 pb3/ ain3 [tim1_ etr] i/o x x x o1 x x port b3 analog input 3 tim1_ etr [afr5] 20 19 14 19 pb2/ ain2 [tim1_ ch3n] i/o x x x o1 x x port b2 analog input 2 tim1_ ch3n [afr5] 21 20 15 20 pb1/ ain1 [tim1_ ch2n] i/o x x x o1 x x port b1 analog input 1 tim1_ ch2n [afr5] 22 21 16 21 pb0/ ain0 [tim1_ ch1n] i/o x x x o1 x x port b0 analog input 0 tim1_ ch1n [afr5] 23 - - - pe7/ ain8 i/o x x x o1 x x port e7 anal og input 8 24 22 - - pe6/ ain9 i/o x x x o1 x x port e6 analog input 9 (3) 25 23 17 22 pe5/spi_ nss i/o x x x o1 x x port e5 spi master/slave select 26 24 18 23 pc1/ tim1_ ch1 uart2_ck i/o x x x hs o3 x x port c1 timer 1 ? channel 1/ uart2 synchronous clock 22/ 99 docid14771 rev 13 stm8s105xx pinout and pin description pin number pin name type input output main function (after reset) default alternate function alternate func tion after remap [option bit] lqfp48 lqfp44 lqfp32/ ufqfpn32 sdip32 floating wpu ext. interrupt high sink speed od pp 27 25 19 24 pc2/ tim1_ ch2 i/o x x x hs o3 x x port c2 timer 1 - channel 2 28 26 20 25 pc3/ tim1_ ch3 i/o x x x hs o3 x x port c3 timer 1 - channel 3 2 9 - 21 26 pc4/ tim1_ ch4 i/o x x x hs o3 x port c4 timer 1 - channel 4 30 27 22 27 pc5/ spi_ sck i/o x x x hs o3 x x port c5 spi clock 31 28 - - v ssio_2 s i/o ground 32 29 - - v ddio_2 s i/o power supply 33 30 23 28 pc6/ spi_ mosi i/o x x x hs o3 x x port c6 spi master out/slave in 34 31 24 29 pc7/ spi_ miso i/o x x x hs o3 x x port c7 spi master in/ slave out 35 32 - - pg0 i/o x x o1 x x port g0 36 33 - - pg1 i/o x x o1 x x port g1 37 - - - pe3/ tim1_ bkin i/o x x x o1 x x port e3 timer 1 - break input 38 34 - - pe2/ i 2 c_ sda i/o x x o1 t (4) port e2 i 2 c data 39 35 - - pe1/ i 2 c_ scl i/o x x o1 t (4) port e1 i 2 c clock 40 36 - - pe0/ clk_ cco i/o x x x hs o3 x x port e0 configurable clock output 41 37 25 30 pd0/ tim3_ ch2 [tim1_bkin] [clk_ cco] i/o x x x hs o3 x x port d0 t imer 3 - channel 2 tim1_ bkin [afr3]/ clk_cco [afr2] 42 38 26 31 pd1/ swim (5) i/o x x x hs o4 x x port d1 swim data interface 43 39 27 32 pd2/ tim3_ch1 [tim2_ ch3] i/o x x x hs o3 x x port d2 timer 3 - channel 1 tim2_ch3 [afr1] 44 40 28 1 pd3/ tim2_ch2 [adc_ etr] i/o x x x hs o3 x x port d3 timer 2 - channel 2 a dc_ etr [afr0] 45 41 29 2 pd4/ tim2_ ch1 [beep] i/o x x x hs o3 x x port d4 timer 2 - channel 1 beep ou tput [afr7] 46 42 30 3 pd5/ uart2_ tx i/o x x x o1 x x port d5 uart2 data transmit 47 43 31 4 pd6/ uart2_ rx i/o x x x o1 x x port d6 uart2 data receive 48 44 32 5 pd7/ tli [tim1_ ch4] i/o x x x o1 x x port d7 top level interrupt tim1_ ch4 [afr4] notes: (1) a pull - up is applied to pf4 during the reset phase. this pin is input floating after reset release. (2) ain12 is not selectable in adc scan mode or with analog watchdog. (3) in 44 - pin package, ain9 cann ot be used by adc scan mode. (4) in the open - drain output column, ?t? defines a true open - drain i/o (p - buffer, weak pull - up and protection diode to v dd are not implemented). (5) the pd1 pin is in input pull - up during the reset phase and after internal re set release. docid14771 rev 13 23/ 99 pinout and pin description st m8s105xx 5.1.1 alternate function remapping as shown in the rightmost column of the pin description table, some alternate functions can be remapped at different i/o ports by programming one of eight a fr (alternate function remap) option bits. when the remapping option is active, the default alternate function is no longer available. to use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. alternate funct ion remapping does not affect gpio capabilities of the i/o ports (see the gpio section of the family reference manual, rm0016). 24/ 99 docid14771 rev 13 stm8s105xx memory and register map 6 memory and register map 6.1 memory map figure 7 : memory map the following table lists the boundary addresses for each memory size. the top of the stack is at the ram end address in each case. docid14771 rev 13 25/ 99 memory and register map st m8s105xx table 7: flash, data eeprom and ram boundary addresses memory area size (bytes) s tart address end address flash program memory 32k 0x00 8000 0x00 ffff 16k 0x00 8000 0x00 bfff ram 2k 0x00 0000 0x00 07ff data eeprom 1024 0x00 4000 0x00 43ff 6.2 register map 6.2.1 i/o port hardware regi ster map table 8: i/o port hardware register map address block register label register name reset status 0x00 5000 port a pa_odr port a data output latch register 0x00 0x00 5001 pa_idr port a input pin value register 0xxx 0x00 5002 pa_ddr port a data direction register 0x00 0x00 5003 pa_cr1 port a control register 1 0x00 0x00 5004 pa_cr2 port a control register 2 0x00 0x00 5005 port b pb_odr port b data output lat ch register 0x00 0x00 5006 pb_idr port b input pin value register 0xxx 0x00 5007 pb_ddr port b data direction register 0x00 0x00 5008 pb_cr1 port b control register 1 0x00 0x00 5009 pb_cr2 port b control register 2 0x00 0x00 500a port c pc_odr port c data output latch register 0x00 0x00 500b pc_idr port c input pin value register 0xxx 0x00 500c pc_ddr port c data direction register 0x00 0x00 500d pc_cr1 port c control register 1 0x00 0x00 500e pc_cr2 por t c control register 2 0x00 0x00 500f port d pd_odr port d data output latch register 0x00 0x00 5010 pd_idr port d input pin value register 0xxx 0x00 5011 pd_ddr port d data direction register 0x00 0x00 5012 pd_cr1 port d control re gister 1 0x02 0x00 5013 pd_cr2 port d control register 2 0x00 0x00 5014 port e pe_odr port e data output latch register 0x00 0x00 5015 pe_idr port e input pin value register 0xxx 0x00 5016 pe_ddr port e data direction register 0x00 0x00 5017 pe_cr1 port e control register 1 0x00 0x00 5018 pe_cr2 port e control register 2 0x00 0x00 5019 port f pf_odr port f data output latch register 0x00 26/ 99 docid14771 rev 13 stm8s105xx memory and register map address block register label register name reset status 0x00 501a pf_idr port f input pin value register 0xxx 0x00 501b pf_d dr port f data direction register 0x00 0x00 501c pf_cr1 port f control register 1 0x00 0x00 501d pf_cr2 port f control register 2 0x00 0x00 501e port g pg_odr port g data output latch register 0x00 0x00 501f pg_idr port g input pin value register 0xxx 0x00 5020 pg_ddr port g data direction register 0x00 0x00 5021 pg_cr1 port g control register 1 0x00 0x00 5022 pg_cr2 port g control register 2 0x00 0x00 5023 port h ph_odr port h data output latch register 0x0 0 0x00 5024 ph_idr port h input pin value register 0xxx 0x00 5025 ph_ddr port h data direction register 0x00 0x00 5026 ph_cr1 port h control register 1 0x00 0x00 5027 ph_cr2 port h control register 2 0x00 0x00 5028 port i pi_odr port i data output latch register 0x00 0x00 5029 pi_idr port i input pin value register 0xxx 0x00 502a pi_ddr port i data direction register 0x00 0x00 502b pi_cr1 port i control register 1 0x00 0x00 502c pi_cr2 port i control regi ster 2 0x00 6.2.2 general hardware register map table 9: general hardware register map address block register label register name reset status 0x00 5050 to 0x00 5059 reserved area (10 bytes) 0x 00 505a flash flash_cr1 flash control register 1 0x00 0x00 505b flash_cr2 flash control register 2 0x00 0x00 505c flash_ncr2 flash complementary control register 2 0xff 0x00 505d flash _fpr flash protection register 0x00 0x00 505e flash _nfpr flash complementary protection register 0xff 0x00 505f flash _iapsr flash in - application programming status register 0x00 0x00 5060 to 0x00 5061 reserved area (2 bytes) 0x00 5062 flash flash _pukr flash program memory unprotec tion register 0x00 docid14771 rev 13 27/ 99 memory and register map st m8s105xx address block register label register name reset status 0x00 5063 reserved area (1 byte) 0x00 5064 flash flash _dukr data eeprom unprotection register 0x00 0x00 5065 to 0x00 509f reserved area (59 bytes) 0x00 50a0 itc exti_cr1 external interrupt control register 1 0x00 0x 00 50a1 exti_cr2 external interrupt control register 2 0x00 0x00 50a2 to 0x00 50b2 reserved area (17 bytes) 0x00 50b3 rst rst_sr reset status register 0xxx (1) 0x00 50b4 to 0x00 50bf reserved area (12 bytes) 0x00 50c0 clk clk_ickr internal clock control register 0x01 0x00 50c1 clk_eckr external clock control register 0x00 0x00 50c2 reserved area (1 byte) 0x00 50c3 clk clk_cmsr clock master status register 0xe1 0x00 50c4 clk_swr clock master switch register 0xe1 0x00 50c5 clk_swcr clock switch control register 0xxx 0x00 50c6 clk_ckdivr clock divider register 0x18 0x00 50c7 clk_pckenr1 peripheral clock gating register 1 0xff 0x00 50c8 clk_cssr clock security syst em register 0x00 0x00 50c9 clk_ccor configurable clock control register 0x00 0x00 50ca clk_pckenr2 peripheral clock gating register 2 0xff 0x00 50cb clk_canccr can clock control register 0x00 0x00 50cc clk_hsitrimr hsi clock calibra tion trimming register 0x00 0x00 50cd clk_swimccr swim clock control register 0bxxxx xxx0 0x00 50ce to 0x00 50d0 reserved area (3 bytes) 0x00 50d1 wwdg wwdg_cr wwdg control register 0x7f 0x00 50d2 wwdg_wr wwdr window register 0x7f 0 x00 50d3 to 0x00 50df reserved area (13 bytes) 0x00 50e0 iwdg iwdg_kr iwdg key register 0xxx (2) 0x00 50e1 iwdg_pr iwdg prescaler register 0x00 0x00 50e2 iwdg_rlr iwdg reload register 0xff 0x00 50e3 to 0x00 50ef reserved area (13 bytes) 0x00 50f0 awu awu_csr1 awu control/ status register 1 0x00 28/ 99 docid14771 rev 13 stm8s105xx memory a nd register map address block register label register name reset status 0x00 50f1 awu_apr awu asynchronous prescaler buffer register 0x3f 0x00 50f2 awu_tbr awu timebase selection register 0x00 0x00 50f3 beep bee p_csr beep control/ status register 0x1f 0x00 50f4 to 0x00 50ff reserved area (12 bytes) 0x00 5200 spi spi_cr1 spi control register 1 0x00 0x00 5201 spi_cr2 spi control register 2 0x00 0x00 5202 spi_icr spi interrupt control register 0x00 0x00 5203 spi_sr spi status register 0x02 0x00 5204 spi_dr spi data register 0x00 0x00 5205 spi_crcpr spi crc polynomial register 0x07 0x00 5206 spi_rxcrcr spi rx crc register 0xff 0x00 5207 spi_txcrcr spi tx crc register 0xff 0x00 5208 to 0x00 520f reserved area (8 bytes) 0x00 5210 i 2 c i2c_cr1 i 2 c control register 1 0x00 0x00 5211 i2c_cr2 i 2 c control register 2 0x00 0x00 5212 i2c_freqr i 2 c frequency register 0x00 0x00 5213 i2c_oarl i 2 c own addr ess register low 0x00 0x00 5214 i2c_oarh i 2 c own address register high 0x00 0x00 5215 reserved 0x00 5216 i2c_dr i 2 c data register 0x00 0x00 5217 i2c_sr1 i 2 c status register 1 0x00 0x00 5218 i2c_sr2 i 2 c status register 2 0x00 0x00 5219 i2c_sr3 i 2 c status register 3 0x00 0x00 521a i2c_itr i 2 c interrupt control register 0x00 0x00 521b i2c_ccrl i 2 c clock control register low 0x00 0x00 521c i2c_ccrh i 2 c clock control register high 0x00 0x00 521d i2c_triser i 2 c trise register 0x02 0x00 521e i2c_pecr i 2 c packet error checking register 0x00 0x00 521f to 0x00 522f reserved area (17 bytes) 0x00 5230 to 0x00 523f reserved area (6 bytes) 0x00 5240 uart2 uart2_sr uart2 status register 0xc0 0x 00 5241 uart2_dr uart2 data register 0xxx 0x00 5242 uart2_brr1 uart2 baud rate register 1 0x00 docid14771 rev 13 29/ 99 memory and register map st m8s105xx address block register label register name reset status 0x00 5243 uart2_brr2 uart2 baud rate register 2 0x00 0x00 5244 uart2_cr1 uart2 control register 1 0x00 0x00 5245 uart2_cr2 uart2 contr ol register 2 0x00 0x00 5246 uart2_cr3 uart2 control register 3 0x00 0x00 5247 uart2_cr4 uart2 control register 4 0x00 0x00 5248 uart2_cr5 uart2 control register 5 0x00 0x00 5249 uart2_cr6 uart2 control register 6 0x00 0x00 524a uart2_gtr uart2 guard time register 0x00 0x00 524b uart2_pscr uart2 prescaler register 0x00 0x00 524c to 0x00 524f reserved area (4 bytes) 0x00 5250 tim1 tim1_cr1 tim1 control register 1 0x00 0x00 5251 tim1_cr2 tim1 control registe r 2 0x00 0x00 5252 tim1_smcr tim1 slave mode control register 0x00 0x00 5253 tim1_etr tim1 external trigger register 0x00 0x00 5254 tim1_ier tim1 interrupt enable register 0x00 0x00 5255 tim1_sr1 tim1 status register 1 0x00 0x00 5256 tim1_sr2 tim1 status register 2 0x00 0x00 5257 tim1_egr tim1 event generation register 0x00 0x00 5258 tim1_ccmr1 tim1 capture/ compare mode register 1 0x00 0x00 5259 tim1_ccmr2 tim1 capture/compare mode register 2 0x00 0x00 5 25a tim1_ccmr3 tim1 capture/ compare mode register 3 0x00 0x00 525b tim1_ccmr4 tim1 capture/compare mode register 4 0x00 0x00 525c tim1_ccer1 tim1 capture/ compare enable register 1 0x00 0x00 525d tim1_ccer2 tim1 capture/compare ena ble register 2 0x00 0x00 525e tim1_cntrh tim1 counter high 0x00 0x00 525f tim1_cntrl tim1 counter low 0x00 0x00 5260 tim1_pscrh tim1 prescaler register high 0x00 0x00 5261 tim1_pscrl tim1 prescaler register low 0x00 0x00 5262 tim1_arrh tim1 auto - reload register high 0xff 0x00 5263 tim1_arrl tim1 auto - reload register low 0xff 0x00 5264 tim1_rcr tim1 repetition counter register 0x00 30/ 99 docid14771 rev 13 stm8s105xx memory and register map address block register label register name reset status 0x00 5265 tim1_ccr1h tim1 capture/ compare register 1 high 0x00 0x00 5266 tim1_ccr1l tim1 capture/ compare register 1 low 0x00 0x00 5267 tim1_ccr2h tim1 capture/ compare register 2 high 0x00 0x00 5268 tim1_ccr2l tim1 capture/ compare register 2 low 0x00 0x00 5269 tim1_ccr3h tim1 capture/ compare register 3 hig h 0x00 0x00 526a tim1_ccr3l tim1 capture/ compare register 3 low 0x00 0x00 526b tim1_ccr4h tim1 capture/ compare register 4 high 0x00 0x00 526c tim1_ccr4l tim1 capture/ compare register 4 low 0x00 0x00 526d tim1_bkr tim1 break regis ter 0x00 0x00 526e tim1_dtr tim1 dead - time register 0x00 0x00 526f tim1_oisr tim1 output idle state register 0x00 0x00 5270 to 0x00 52ff reserved area (147 bytes) 0x00 5300 tim2 tim2_cr1 tim2 control register 1 0x00 0x00 5301 tim 2_ier tim2 interrupt enable register 0x00 0x00 5302 tim2_sr1 tim2 status register 1 0x00 0x00 5303 tim2_sr2 tim2 status register 2 0x00 0x00 5304 tim2_egr tim2 event generation register 0x00 0x00 5305 tim2_ccmr1 tim2 capture/ compa re mode register 1 0x00 0x00 5306 tim2_ccmr2 tim2 capture/ compare mode register 2 0x00 0x00 5307 tim2_ccmr3 tim2 capture/ compare mode register 3 0x00 0x00 5308 tim2_ccer1 tim2 capture/ compare enable register 1 0x00 0x00 5309 ti m2_ccer2 tim2 capture/ compare enable register 2 0x00 0x00 530a tim2_cntrh tim2 counter high 0x00 0x00 530b tim2_cntrl tim2 counter low 0x00 0x00 530c tim2_pscr tim2 prescaler register 0x00 0x00 530d tim2_arrh tim2 auto - reload regi ster high 0xff 0x00 530e tim2_arrl tim2 auto - reload register low 0xff docid14771 rev 13 31/ 99 memory and register map st m8s105xx address block register label register name reset status 0x00 530f tim2_ccr1h tim2 capture/ compare register 1 high 0x00 0x00 5310 tim2_ccr1l tim2 capture/ compare register 1 low 0x00 0x00 5311 tim2_ccr2h tim2 capture/ compare reg. 2 high 0x00 0x00 5312 tim2_ccr2l tim2 capture/ compare register 2 low 0x00 0x00 5313 tim2_ccr3h tim2 capture/ compare register 3 high 0x00 0x00 5314 tim2_ccr3l tim2 capture/ compare register 3 low 0x00 0x00 5315 to 0x00 53 1f reserved area (11 bytes) 0x00 5320 tim3 tim3_cr1 tim3 control register 1 0x00 0x00 5321 tim3_ier tim3 interrupt enable register 0x00 0x00 5322 tim3_sr1 tim3 status register 1 0x00 0x00 5323 tim3_sr2 tim3 status register 2 0x00 0x00 5324 tim3_egr tim3 event generation register 0x00 0x00 5325 tim3_ccmr1 tim3 capture/ compare mode register 1 0x00 0x00 5326 tim3_ccmr2 tim3 capture/ compare mode register 2 0x00 0x00 5327 tim3_ccer1 tim3 capture/ compare enable register 1 0x00 0x00 5328 tim3_cntrh tim3 counter high 0x00 0x00 5329 tim3_cntrl tim3 counter low 0x00 0x00 532a tim3_pscr tim3 prescaler register 0x00 0x00 532b tim3_arrh tim3 auto - reload register high 0xff 0x00 532c tim3_arr l tim3 auto - reload register low 0xff 0x00 532d tim3_ccr1h tim3 capture/ compare register 1 high 0x00 0x00 532e tim3_ccr1l tim3 capture/ compare register 1 low 0x00 0x00 532f tim3_ccr2h tim3 capture/ compare register 2 high 0x00 0x00 5 330 tim3_ccr2l tim3 capture/ compare register 2 low 0x00 0x00 5331 to 0x00 533f reserved area (15 bytes) 0x00 5340 tim4 tim4_cr1 tim4 control register 1 0x00 0x00 5341 tim4_ier tim4 interrupt enable register 0x00 32/ 99 docid14771 rev 13 stm8s105xx memory and regis ter map address block register label register name reset status 0x00 5342 tim4_sr t im4 status register 0x00 0x00 5343 tim4_egr tim4 event generation register 0x00 0x00 5344 tim4_cntr tim4 counter 0x00 0x00 5345 tim4_pscr tim4 prescaler register 0x00 0x00 5346 tim4_arr tim4 auto - reload register 0xff 0x00 5347 to 0x00 53df reserved area (153 bytes) 0x00 53e0 to 0x00 53f3 adc1 adc _dbxr adc data buffer registers 0x00 0x00 53f4 to 0x00 53ff reserved area (12 bytes) 0x00 5400 adc1 adc _csr adc control/ status register 0x00 0x00 5401 adc_cr1 adc c onfiguration register 1 0x00 0x00 5402 adc_cr2 adc configuration register 2 0x00 0x00 5403 adc_cr3 adc configuration register 3 0x00 0x00 5404 adc_drh adc data register high 0xxx 0x00 5405 adc_drl adc data register low 0xxx 0x00 5406 adc_tdrh adc schmitt trigger disable register high 0x00 0x00 5407 adc_tdrl adc schmitt trigger disable register low 0x00 0x00 5408 adc_htrh adc high threshold register high 0x03 0x00 5409 adc_htrl adc high threshold register low 0xff 0x00 540a adc_ltrh adc low threshold register high 0x00 0x00 540b adc_ltrl adc low threshold register low 0x00 0x00 540c adc_awsrh adc analog watchdog status register high 0x00 0x00 540d adc_awsrl adc analog watchdog status register low 0x00 0x00 540e adc _awcrh adc analog watchdog control register high 0x00 0x00 540f adc_awcrl adc analog watchdog control register low 0x00 0x00 5410 to 0x00 57ff reserved area (1008 bytes) notes: (1) depends on the previou s reset source. (2) write only register. docid14771 rev 13 33/ 99 memory and register map st m8s105xx 6.2.3 cpu/swim/debug module/interrupt controller registers table 10: cpu/swim/debug module/interrupt controller registers address block register label register name reset status 0x00 7f00 cpu (1) a accumulator 0x00 0x00 7f01 pce program counter extended 0x00 0x00 7f02 pch program counter high 0x00 0x00 7f03 pcl program counter low 0x00 0x00 7f04 xh x index register high 0x00 0x00 7f05 xl x index register low 0x00 0x00 7f06 yh y index register high 0x00 0x00 7f07 yl y index register low 0x00 0x00 7f08 sph stack pointer high 0x07 0x00 7f09 spl stack pointer low 0xff 0x00 7f0a ccr condition code register 0x28 0x00 7f0b to 0x00 7f5f reserved area (85 bytes) 0x00 7f60 cpu cfg_gcr global configuration register 0x00 0x00 7f70 itc itc_spr1 interrupt software priority register 1 0xff 0x00 7f71 itc_spr2 interrupt software priority register 2 0xff 0x00 7f72 itc_spr3 interrupt software priority register 3 0xff 0x00 7f73 itc_spr4 interrupt software priority register 4 0xff 0x00 7f74 itc_spr5 interrupt software priority register 5 0xff 0x00 7f75 itc_spr6 interrupt software priority register 6 0xff 0x00 7f76 itc_spr7 interrupt software priority register 7 0xff 0x00 7f77 itc_spr8 interrupt software priority register 8 0xff 0x00 7f78 to 0x00 7f79 reser ved area (2 bytes) 0x00 7f80 swim swim_csr swim control status register 0x00 0x00 7f81 to 0x00 7f8f reserved area (15 bytes) 0x00 7f90 dm dm_bk1re dm breakpoint 1 register extended byte 0xff 0x00 7f91 dm_bk1rh dm breakpoint 1 register h igh byte 0xff 0x00 7f92 dm_bk1rl dm breakpoint 1 register low byte 0xff 0x00 7f93 dm_bk2re dm breakpoint 2 register extended byte 0xff 0x00 7f94 dm_bk2rh dm breakpoint 2 register high byte 0xff 0x00 7f95 dm_bk2rl dm breakpoint 2 reg ister low byte 0xff 0x00 7f96 dm_cr1 dm debug module control 0x00 34/ 99 docid14771 rev 13 stm8s105xx memory and register map address block register label register name reset status register 1 0x00 7f97 dm_cr2 dm debug module control register 2 0x00 0x00 7f98 dm_csr1 dm debug module control/status register 1 0x10 0x00 7f99 dm_csr2 dm debug module control/status register 2 0x00 0x00 7f9a dm_enfctr dm enable function register 0xff 0x00 7f9b to 0x00 7f9f reserved area (5 bytes) notes: (1) accessible by debug module only docid14771 rev 13 35/ 99 interrupt vector mapping st m8s105xx 7 interrupt vector mapping table 11: interrupt mapping irq no. source block description wakeup from halt mode wakeup from active - halt mode vector address reset reset yes yes 0x00 8000 trap software interrupt - - 0x00 8004 0 tli external top level interrupt - - 0x00 8008 1 awu auto wak e up from halt - yes 0x00 800c 2 clk clock controller - - 0x00 8010 3 exti0 port a external interrupts yes (1) yes (1) 0x00 8014 4 exti1 port b external interrupts yes yes 0x00 8018 5 exti2 port c external interrupts yes yes 0x00 801c 6 exti3 port d external interrupts yes yes 0x00 8020 7 exti4 port e external interrupts yes yes 0x00 8024 8 0x00 8028 9 reserved - - 0x00 802c 10 spi end of transfer yes yes 0x00 8030 11 tim1 tim1 update/ overflow/ underflow/ trigger/ break - - 0x00 8034 12 tim1 tim1 capture/ compare - - 0x00 8038 13 tim2 tim update/ overflow - - 0x00 803c 14 tim2 tim capture/ compare - - 0x00 8040 15 tim3 update/ overflow - - 0x00 8044 16 tim3 capture/ compare - - 0x00 8048 17 reserved - - 0x00 804c 18 reserved - - 0x00 8050 19 i 2 c i 2 c interrupt yes yes 0x00 8054 20 uart2 tx complete - - 0x00 805 8 21 uart2 receive register data full - - 0x00 805c 22 adc1 adc1 end of conversion/ analog watchdog interrupt - - 0x00 8060 23 tim4 tim update/ overflow - - 0x00 8064 24 flash eop/ wr_pg_dis - - 0x00 8068 reserved 0x00 806c to 0x00807c notes: (1) except pa1 36/ 99 docid14771 rev 13 stm8s105xx option bytes 8 option bytes option bytes contain configurations for device hardware features as well as the memory protection of the device. they are stored in a dedicated block of the memory. except for the rop (read - out protection) byte, each option byte has to be stored twice, in a regular form (optx) and a complemented one (noptx) for redundancy. option bytes can be modified in icp mode (via swim) by accessing the eeprom address shown in th e table below. option bytes can also be modified ?on the fly? by the application in iap mode, except the rop option that can only be modified in icp mode (via swim). refer to the stm8s flash programming manual (pm0051) and stm8 swim communication protoco l and debug module user manual (um0470) for information on swim programming procedures. table 12: option bytes addr. option name option byte no. option bits factory default setting 7 6 5 4 3 2 1 0 0x4800 read - out protection (rop) opt 0 rop [7:0] 00h 0x4801 user boot code(ubc) opt1 ubc [7:0] 00h 0x4802 nopt1 nubc [7:0] ffh 0x4803 alternate function remapping (afr) opt2 afr7 afr6 afr5 afr4 afr3 afr2 afr1 afr0 00h 0x4804 nopt2 nafr7 nafr6 nafr5 nafr4 na fr3 nafr2 nafr1 nafr0 ffh 0x4805h miscell. option opt3 reserved hsi trim lsi_ en iwdg _hw wwdg _hw wwdg _halt 00h 0x4806 nopt3 reserved nhsi trim nlsi_ en niwdg _hw nwwdg _hw nww g_halt ffh 0x4807 clock option opt4 reserved ext clk ckawu sel prs c1 prs c0 00h 0x4808 nopt4 reserved next clk ncka wusel nprsc1 npr sc0 ffh 0x4809 hse clock startup opt5 hsecnt [7:0] 00h 0x480a nopt5 nhsecnt [7:0] ffh 0x480b reserved opt6 reserved 00h 0x480c nopt 6 reserved ffh 0x480d reserved opt7 reserved 00h 0x480e nopt7 reserved ffh 0x480f - 0x48fd reserved 0x487e bootloader optbl bl[7:0] 00h docid14771 rev 13 37/ 99 option bytes st m8s105xx addr. option name option byte no. option bits factory default setting 7 6 5 4 3 2 1 0 0x487f noptbl nbl[7:0] table 13: option byte description option byte no. descrip tion opt0 rop[7:0] memory readout protection (rop) aah: enable readout protection (write access via swim protocol) note: refer to the family reference manual (rm0016) section on flash/eeprom memory readout protection for details. opt1 ubc[7:0] user boot code area 0x00: no ubc, no write - protection 0x01: page 0 to 1 defined as ubc, memory write - protected 0x02: page 0 to 3 defined as ubc, memory write - protected 0x03: page 0 to 4 defined as ubc, memory write - protected ... 0x3e: pages 0 to 63 defin ed as ubc, memory write - protected other values: reserved note: refer to the family reference manual (rm0016) section on flash write protection for more details. opt2 afr[7:0] refer to following table for the alternate function remapping decriptions o f bits [7:2]. opt3 hsitrim :high speed internal clock trimming register size 0: 3 - bit trimming supported in clk_hsitrimr register 1: 4 - bit trimming supported in clk_hsitrimr register lsi_en :low speed internal clock enable 0: lsi clock is not availa ble as cpu clock source 1: lsi clock is available as cpu clock source iwdg_hw : independent watchdog 0: iwdg independent watchdog activated by software 1: iwdg independent watchdog activated by hardware wwdg_hw : window watchdog activation 0: wwdg window watchdog activated by software 1: wwdg window watchdog activated by hardware wwdg_halt : window watchdog reset on halt 0: no reset generated on halt if wwdg active 1: reset generated on halt if wwdg active opt4 extclk : external clock selecti on 0: external crystal connected to oscin/oscout 1: external clock signal on oscin ckawusel :auto wake - up unit/clock 0: lsi clock source selected for awu 1: hse clock with prescaler selected as clock source for for awu 38/ 99 docid14771 rev 13 stm8s105xx option bytes option byte no. descrip tion prsc[1:0] awu clock prescale r 0x: 16 mhz to 128 khz prescaler 10: 8 mhz to 128 khz prescaler 11: 4 mhz to 128 khz prescaler opt5 hsecnt[7:0] :hse crystal oscillator stabilization time 0x00: 2048 hse cycles 0xb4: 128 hse cycles 0xd2: 8 hse cycles 0xe1: 0.5 hse cycles opt6 reserved opt7 reserved optbl bl[7:0] bootloader option byte for stm8s products, this option is checked by the boot rom code after reset. depending on the content of addresses 0x487e, 0x487f, and 0x8000 (reset vector), the cpu jumps to the bootloader or to the reset vector. refer to the um0560 (stm8l/s bootloader manual) for more details. for stm8l products, the bootloader option bytes are on addresses 0xxxxx and 0xxxxx+1 (2 bytes). these option bytes control whether the bootloader is active or not. for more details, refer to the um0560 (stm8l/s bootloader manual) for more details. table 14: description of alternate function remapping bits [7:0] of opt2 option byte no. description (1) opt2 afr7 alternate functi on remapping option 7 0: afr7 remapping option inactive: default alternate function (2) . 1: port d4 alternate function = beep. afr6 alternate function remapping option 6 0: afr6 remapping option inactive: default alte rnate functions (2) . 1: port b5 alternate function = i 2 c_sda; port b4 alternate function = i 2 c_scl. afr5 alternate function remapping option 5 0: afr5 remapping option inactive: default alternate functions (2) . 1: port b3 alternate function = tim1_etr; port b2 alternate function = tim1_ncc3; port b1 alternate function = tim1_ch2n; port b0 alternate function = tim1_ch1n. afr4 alternate function remapping option 4 0: afr4 remapping op tion inactive: default alternate function (2) . 1: port d7 alternate function = tim1_ch4. afr3 alternate function remapping option 3 0: afr3 remapping option inactive: default alternate function (2) . 1: port d0 alternate function = tim1_bkin. afr2 alternate function remapping option 2 0: afr2 remapping option inactive: default alternate function (2) . 1: port d0 alternate function = clk_cco. note: af r2 option has priority over afr3 if both are activated. afr1 alternate function remapping option 1 0: afr1 remapping option inactive: default alternate functions (2) . docid14771 rev 13 39/ 99 option bytes st m8s105xx option byte no. description (1) 1: port a3 alternate function = tim3_ch1; port d2 a lternate function tim2_ch3. afr0 alternate function remapping option 0 0: afr0 remapping option inactive: default alternate function (2) . 1: port d3 alternate function = adc_etr. notes: (1) do not use more than one remapping option in the same port. (2) refer to pinout description. 40/ 99 docid14771 rev 13 stm8s105xx unique id 9 unique id the devices feature a 96 - bit unique device identifier which provides a reference number that is unique for any device and in any context. the 96 bits of the identifier can never be altered by the user. the unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm. the unique device identifier is ideally suited: ? for use as serial numbers ? fo r use as security keys to increase the code security in the program memory while using and combining this unique id with software cryptographic primitives and protocols before programming the internal memory. ? to activate secure boot processes table 15: u nique id registers (96 bits) address content description unique id bits 7 6 5 4 3 2 1 0 0x48cd x co - ordinate on the wafer u_id[7:0] 0x48ce u_id[15:8] 0x48cf y co - ordinate on the wafer u_id[23:16] 0x48d0 u_i d[31:24] 0x48d1 wafer number u_id[39:32] 0x48d2 lot number u_id[47:40] 0x48d3 u_id[55:48] 0x48d4 u_id[63:56] 0x48d5 u_id[71:64] 0x48d6 u_id[79:72] 0x48d7 u_id[87:80] 0x48d8 u_id[95:88] docid14771 rev 13 41/ 99 electrical characteristics st m8s105xx 10 electrical charact eristics 10.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 10.1.1 minimum and maximum values unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at t a = 25 c an d t a = t amax (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minim um and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 10.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 5 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ). 10.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 10.1.4 typical current consumption for typical current consumption measurements, v dd , v ddio and v dda are connected together in the configuration shown in the following figure. figure 8 : supply current measurement co nditions 42/ 99 docid14771 rev 13 stm8s105xx electrical characteristics 10.1.5 loading capacitor the loading conditions used for pin parameter measurement are shown in the following figure. figure 9 : pin loading conditions 10.1.6 pin input voltage the input voltage measurement on a pin of the device is described in the following figure. figure 10 : pin input voltage 10.2 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extend ed periods may affect device reliability. table 16: voltage characteristics symbol ratings min max unit v ddx - v ss supply voltage (including v dda and v ddio ) (1) - 0.3 6.5 v v in input voltage on true open drain p ins (pe1, pe2) (2) v ss - 0.3 6.5 input voltage on any other pin (2) v ss - 0.3 v dd + 0.3 |v ddx - variations between different power 50 mv docid14771 rev 13 43/ 99 electrical characteristics st m8s105xx symbol ratings min max unit v dd | pins |v ssx - v ss | variations between all the different ground pins 50 v esd electrostatic discharge voltage see section 13.3.12.4: "absolute maximum ratings (electrical sensitivity)" notes: (1) all power (v dd , v ddio , v dda ) and ground (v ss , v ssi o , v ssa ) pins must always be connected to the external power supply (2) i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in electrical characteristics st m8s105xx figure 11 : fcpumax versus vdd table 20: operating conditions at power - up/power - down symbol parameter conditions min typ max unit t vdd v dd rise time rate 2.0 (1) s/v v dd fall time rate 2.0 (1) t temp reset releasedelay v dd rising 1.7 (1) ms v it+ power - on reset threshold 2.65 2.8 2.95 v v it - brown - out reset threshold 2 .58 2.7 2.88 v hys(bor) brown - out reset hysteresis 70 mv notes: (1) guaranteed by design, not tested in production. 10.3.1 vcap external capacitor stabilization for the main regulator is achieved co nnecting an external capacitor c ext to the v cap pin. c ext is specified in the operating conditions section. care should be taken to limit the series inductance to less than 15 nh. 46/ 99 docid14771 rev 13 stm8s105xx electrical characteristics figure 12 : external capacitor cext 1. esr is the eq uivalent series resistance and esl is the equivalent inductance. 10.3.2 supply current characteristics the current consumption is measured as described in section 7.3: "inte rrupt controller" . 10.3.2.1 total current consumption in run mode table 21: total current consumption with code execution in run mode at vdd = 5 v symbol parameter conditions typ max (1) unit i dd(run) supply current in run mode, code executed from ram f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 3.2 ma hse user ext. clock (16 mhz) 2.6 3.2 hsi rc osc. (16 mhz) 2.5 3.2 f cpu = f maste r /128 = 125 khz hse user ext. clock (16 mhz) 1.6 2.2 hsi rc osc. (16 mhz) 1.3 2.0 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mh3z/8) 0.75 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.55 i dd(run) supply current in run mode, code executed from flash f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 7.7 hse user ext. clock (16 mhz) 7.0 8.0 hsi rc osc. (16 mhz) 7.0 8.0 f cpu = f master hsi rc osc. 1.5 docid14771 rev 13 47/ 99 electrical characteristics st m8s105xx symbol parameter conditions typ max (1) unit = 2 mhz (16 mhz/8) (2) f cpu = f master /128 = 125 khz hsi rc osc. (16 mhz) 1.35 2.0 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) 0.75 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.6 notes: (1) data based on character ization results, not tested in production. (2) default clock configuration measured with all peripherals off. table 22: total current consumption with code execution in run mode at vdd = 3.3 v symbol parameter conditions typ max (1) unit i dd(run) supply current in run mode, code executed from ram f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 2.8 ma hse user ext. clock (16 mhz) 2.6 3.2 hsi rc osc. (16 mhz) 2.5 3.2 f cpu = f master /128 = 125 khz hse user ext. clock (16 mhz) 1.6 2.2 hsi rc osc. (16 mhz) 1.3 2.0 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) 0.75 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.55 supply current in run mode, code executed from flash f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 7.3 hse user ext. clock (16 mhz) 7.0 8.0 hsi rc osc. (16 mhz) 7.0 8.0 f cpu = f master = 2 mhz hsi rc osc. (16 mhz/8) (2) 1.5 48/ 99 docid14771 rev 13 stm8s105xx electrical characteristics symbol parameter conditions typ max (1) unit f cpu = f master /128 = 125 khz hsi rc osc. (16 mhz) 1.35 2.0 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) 0.75 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.6 notes: (1) data based on characterization results , not tested in production. (2) default clock configuration measured with all peripherals off. 10.3.2.2 total current consumption in wait mode table 23: total current consumption in wait mode at vdd = 5 v symbol parameter conditions typ max (1) unit i dd(wfi) supply current in wait mode f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 2.15 ma hse user ext. clock (16 mhz) 1.55 2.0 hsi rc osc. (16 mhz) 1.5 1.9 f cpu = f master /128 = 125 khz hsi rc osc. (16 mhz) 1.3 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) (2) 0.7 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.5 no tes: (1) data based on characterization results, not tested in production. (2) default clock configuration measured with all peripherals off. table 24: total current consumption in wait mode at vdd = 3.3 v symbol parameter conditions typ max (1) unit i dd(wfi) supply current in wait mode f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 1.75 ma hse user ext. clock 1.55 2.0 docid14771 rev 13 49/ 99 electrical characteristics st m8s105xx symbol parameter conditions typ max (1) unit (16 mhz) hsi rc osc. (16 mhz) 1.5 1.9 f cpu = f master /128 = 125 k hz hsi rc osc. (16 mhz) 1.3 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) (2) 0.7 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.5 notes: (1) data based on characterization results, not tested in production. (2) default clock configuration measured with all peripherals off. 10.3.2.3 total current consumption in active halt mode table 25: total current consumption in active h alt mode at vdd = 5 v symbol parameter conditions typ max at 85 c (1) max at 125 c (1) unit main voltage regulator (mvr) (2) flash mode (3) clock source i dd(ah) supply current in active halt mode on operating mode hse crystal osc. (16 mhz) 1080 a lsi rc osc. (128 khz) 200 320 400 power - down mode hse crystal osc. (16 mhz) 1030 lsi rc osc. (128 khz) 140 270 350 off operating mode lsi rc osc. (128 khz) 68 120 220 power - down mode 12 60 150 50/ 99 docid14771 rev 13 stm8s105xx electrical characteristics notes: (1) data based on characterization results, not tested in production (2) configured by the regah b it in the clk_ickr register. (3) configured by the ahalt bit in the flash_cr1 register. table 26: total current consumption in active halt mode at vdd = 3.3 v symbol parameter conditions typ max at 85 c (1) max a t 125 c (1) unit main voltage regulator (mvr) (2) flash mode (3) clock source i dd(ah) supply current in active halt mode on operating mode hse crystal osc. (16 mhz) 680 a lsi rc osc. (128 khz) 200 320 400 power - down mode hse crystal osc. (16 mhz) 630 lsi rc osc. (128 khz) 140 270 350 off operating mode lsi rc osc. (128 khz) 66 120 220 powe r- down mode 10 60 150 notes: (1) data based on characterization results, not tested in production. (2) configured by the regah bit in the clk_ickr register. (3) configured by the ahalt bit in the flash_cr1 register. 10.3.2.4 total current consumption i n halt mode table 27: total current consumption in halt mode at vdd = 5 v symbol parameter conditions typ max at 85 c (1) max at 125 c (1) unit i dd(h) supply current in halt mode flash in operating mode, hsi clock after wakeup 62 90 150 a flash in powerdown mode, hsi clock after wakeup 6.5 25 80 notes: (1) data based on characterization results, not tes ted in production. docid14771 rev 13 51/ 99 electrical characteristics st m8s105xx table 28: total current consumption in halt mode at vdd = 3.3 v symbol parameter conditions typ max at 85 c (1) max at 125 c (1) unit i dd(h) supply current in halt mode flash in operating mode, hsi clock after wakeup 60 90 150 a flash in powerdown mode, hsi clock after wakeup 4.5 20 80 notes: (1) data based on characterization results, not tested in production. 10.3.2.5 low power mode wakeup times table 29: wakeup times symbol parameter conditions typ max (1) unit t wu(wfi) wakeup time from wait mode to run mode (2 ) 0 to 16 mhz see note (3) s f cpu = f master = 16 mhz 0.56 t wu(ah) wakeup time active halt mode to run mode (2) mvr voltage regulator on (4) flash in operating mode (5) hsi (after wakeup) 1 (6) 2 (6) wakeup time active halt mode to run mode (2) mvr voltage regulator on (4) flash in power - down mode (5) hsi (after wakeup) 3 (6) wakeup time active halt mode to run mode (2) mvr voltage regulator off (4) flash in operating mode (5) hsi (after wakeup) 48 (6) wakeup time ac tive halt mode to run mode (2) mvr voltage regulator off (4) flash in power - down mode (5) hsi (after wakeup) 50 (6) t wu(h) wakeup time from halt mode to run mode (2) flash in operating mode (5) 52 flash in power - down mode (5) 54 notes : (1) data guaranteed by design, not tested in production. (2) measured from interrupt event to interrupt vector fetch. (3) t wu(wfi) = 2 x 1/f master + 67 x 1/f cpu. (4) configured by the regah bit in the clk_ickr register. (5) configured by the ahalt bit in the flash_cr1 register. 52/ 99 docid14771 rev 13 stm8s105xx electrical characteristics (6) plus 1 lsi clock depending on synchronization. 10.3.2.6 total current consumption and timing in forced reset state table 30: total current consumpti on and timing in forced reset state symbol parameter conditions typ max (1) unit i dd(r) supply current in reset state (2) v dd = 5 v 500 a v dd = 3.3 v 400 t resetbl reset pin release to vector fetch 150 s notes: (1) data guaranteed by design, not tested in production. (2) characterized with all i/os tied to v ss . 10.3.2.7 current consumption of on - chip peripherals subject to general operating conditions for v dd and t a . hsi internal rc/f cpu = f master = 16 mhz. table 31: peripheral current consumption symbol parameter typ. unit i dd(tim1) tim1 supply current (1) 230 a i dd(tim2) tim2 supply current (1) 115 i dd(tim3) tim3 timer supply current (1) 90 i dd(tim4) tim4 timer supply current (1) 30 i dd(uart2) uart2 supply current (2) 110 i dd(spi) spi supply current (2) 45 i dd(i 2 c) i 2 c supply current (2) 6 5 i dd(adc1) adc1 supply current when converting (3) 955 notes: (1) data based on a differential i dd measurement between reset configuration and timer counter running at 16 mhz. no ic/oc programmed (no i/o pads togg ling). not tested in production. (2) data based on a differential i dd measurement between the on- chip peripheral when kept under reset and not clocked and the on - chip peripheral when clocked and not kept under reset. no i/o pads toggling. not tested in pr oduction. (3) data based on a differential i dd measurement between reset configuration and continuous a/d conversions. not tested in production. 10.3.2.8 current consumption curves the following figures show typical current consumption measured with code executing in ram. docid14771 rev 13 53/ 99 electrical character istics st m8s105xx figure 13 : typ. idd(run) vs. vdd, hse user external clock, fcpu = 16 mhz figure 14 : typ. idd(run) vs. fcpu, hse user external clock, vdd= 5 v figure 15 : typ. idd(run) vs. vdd, hsi rc osc, fcpu = 16 mhz 54/ 99 docid14771 rev 13 stm8s105xx electrical characteristics figure 16 : typ. idd(wfi) vs. vdd, hse user external clock, fcpu = 16 mhz figure 17 : typ. idd(wfi) vs. fcpu, hse user external clock vdd = 5 v figure 18 : typ. idd(wfi) vs. vdd, hsi rc osc, fcpu = 16 mhz docid14771 rev 13 55/ 99 electrical characteristics st m8s105xx 10.3.3 external clock sources and timing characteristics hse user exter nal clock subject to general operating conditions for v dd and t a . table 32: hse user external clock characteristics symbol parameter conditions min max unit f hse_ext user external clock source frequency 0 16 mhz v hseh (1) oscin input pin high level voltage 0.7 x v dd v dd + 0.3 v v v hsel (1) oscin input pin low level voltage v ss 0.3 x v dd i leak_hse oscin input leakage current v ss < v in < v dd -1 +1 a notes: (1) data based on characterization results, not tested in production. figure 19 : hse external clocksource hse crystal/ceramic resonator oscillator the hse clock can be supplied with a 1 to 16 mhz crystal/ceramic resonator oscillator. all the information given in this paragraph is based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscil lator pins in order to minimize output distortion and start - up stabilization time. refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). table 33: hse oscillator characteristics symbol parameter conditions min typ max unit f hse external high speed oscillator frequency 1 16 mhz r f feedback resistor 220 k? 56/ 99 docid14771 rev 13 stm8s105xx electrical characteristics symbol parameter conditions min typ max unit c (1) recommended load capacitance (2) 20 pf i dd(hse) hse oscillator power consumption c = 20 pf, f osc = 16 mhz 6 (startup) 1.6 (stabilized) (3) ma c = 10 pf, f osc =16 mhz 6 (startup) 1.2 (stabilized) (3) g m oscillator transconductance 5 ma/v t su(hse) (4) startup time v dd is stabilized 1 ms notes: (1) c is approximately equivalent to 2 x crystal cload. (2) the oscillator selection can be optimized in terms of supply current using a high quality resonator with small r m value. refer to crystal manufacturer for more details (3) data based on characterization results, not tested in production. (4) t su(hse) is the start- up time measured from the moment it is enabled (by software) to a stabilized 16 mhz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. figure 20 : hse oscillator circuit diag ram hse oscillator critical g m equation g mcrit = (2 f hse ) 2 r m (2co + c) 2 r m : notional resistance (see crystal specification) l m : notional inductance (see crystal specification) c m : notional capacitance (see crystal specification) co: shunt capac itance (see crystal specification) c l1 = c l2 = c: grounded external capacitance g m >> g mcrit docid14771 rev 13 57/ 99 electrical characteristics st m8s105xx 10.3.4 internal clock sources and timing characteristics subject to general operating conditions for v dd and t a . high speed internal rc oscillator (hsi) table 34: hsi oscillator characteristics symbol parameter conditions min typ max unit f hsi frequency 16 mhz acc hsi accuracy of hsi oscillator user - trimmed with clk_hsitrimr register for given v dd and t a conditions (1) 1.0 (2) % accuracy of hsi oscillator (factory calibrated) v dd = 5 v, t a = 25c (3) - 1.0 1.0 v dd = 5 v, 25 c t a 85 c - 2.0 2.0 2.95 v dd 5.5 v, - 40 c t a 125 c - 3.0 (3) 3.0 (3) t su(hsi) hsi oscillator wake - up time including calibration 1.0 (2) s i dd(hsi) hsi oscillator power consumption 170 250 (3) a notes: (1) refer to application note. (2) guaranteed by design, not tested in production. (3) data based on characterization result s, not tested in production. figure 21 : typical hsi accuracy at vdd = 5 v vs 5 temperatures 58/ 99 docid14771 rev 13 stm8s105xx electrical characteristics figure 22 : typical hsi accuracy vs vdd @ 4 temperatures low speed internal rc oscillator (lsi) subject to g eneral operating conditions for v dd and t a . table 35: lsi oscillator characteristics symbol parameter min typ max unit f lsi frequency 110 128 146 khz t su(lsi) lsi oscillator wakeup time 7 (1) s i dd(lsi ) lsi oscillator power consumption 5 a notes: (1) guaranteed by design, not tested in production. figure 23 : typical lsi accuracy vs vdd @ 4 temperatures docid14771 rev 13 59/ 99 electrical characteristics st m8s105xx 10.3.5 memory characteristics ram and hardware registers table 36: ram and hardware registers symbol parameter conditions min unit v rm data retention mode (1) halt mode (or reset) v it - max (2) v notes : (1) minimum supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware registers (only in halt mode). guaranteed by design, not tested in production. refer to section 7.10: "tim1 - 16- bit advanced control timer" for the value of v it - max (2) refer to the operating conditions section for the value of v it - max flash program memory/data eeprom memory general conditions: t a = - 40 to 125c. table 37: flash program memory/data eeprom memory sy mbol parameter conditions min (1) typ max unit v dd operating voltage (all modes, execution/write/erase) f cpu 16 mhz 2.95 5.5 v t prog standard programming time (including erase) for byte/word/block (1 byte/4 bytes/128 bytes) 6.0 6.6 ms fast programming time for 1 block (128 bytes) 3.0 3.3 ms t erase erase time for 1 block (128 bytes) 3.0 3.3 ms n rw erase/write cycles (2) (program memory) t a = +85 c 10 k cycles erase/write cycles(data memory) (2) t a = +125 c 300 k 1.0m t ret data retention (program memo ry) after 10k erase/write cycles at t a = +85 c t ret = 55 c 20 years data retention (data memory) after 10k erase/write cycles at t a = +85 c t ret = 55 c 20 data retention (data memory) after 300 k erase/write cycles at t a = +125 c t ret = 85 c 1.0 i dd supply current (flash programming or erasing for 1 to 128 bytes) 2.0 ma notes: (1) data based on characterization results, not tested in production. (2) the physical granularity of the memory is 4 bytes, so cycling is perfor med on 4 bytes even when a write/erase operation addresses a single byte. 60/ 99 docid14771 rev 13 stm8s105xx electrical characteristics 10.3.6 i/o port pin characteristics general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull - up or pull - down resistor. table 38: i/o static characteristics symbol parameter conditions min typ max unit v il input low level voltage v dd = 5 v - 0.3 0.3 x v dd v v ih input high level voltage 0.7 x v dd v dd + 0.3 v v v hys hysteresis (1) 700 mv r pu pull - up resistor v dd = 5 v, v in = v ss 30 55 80 k t r , t f rise and fall time(10 % - 90 %) fast i/os load = 50 pf 35 (2) standard and high sink i/os l oad = 50 pf 125 (2) ns fast i/os load = 20 pf 20 (2) standard and high sink i/os l oad = 20 pf 50 (2) i lkg input leakage current, analog and digital v ss v in v dd 1.0 (3) a i lkg ana analog input leakage current v ss v in v dd 250 (3) na i lkg(inj) leakage current in adjacent i/o (3) injection current 4 ma 1.0 (3) a notes: (1 ) hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested in production. (2) data guaranteed by design. (3) data based on characterization results, not tested in production. docid14771 rev 13 61/ 99 electrical characteristics st m8s105xx figure 24 : typical vil and vih vs vdd @ 4 temperatures figure 25 : typical pull - up resistance vs vdd @ 4 temperatures 62/ 99 docid14771 rev 13 stm8s105xx electrical characteristics figure 26 : typical pull - up current vs vdd @ 4 temperatures 1. the pull - up is a pure res istor (slope goes through 0). table 39: output driving current (standard ports) symbol parameter conditions min max unit v ol output low level with four pins sunk i io = 4 ma, v dd = 3.3 v 1.0 (1) v output low level with eight pins sunk i io = 10 ma, v dd = 5 v 2.0 v oh output high level with four pins sourced i io = 4 ma, v dd = 3.3 v 2.0 (1) v output high level with eight pins sourced i io = 10 ma, v dd = 5 v 2.4 notes: (1) data based on characterization results, not tested in production table 40: output driving current (true open drain ports) symbol parameter conditions max unit v ol output low level with two pins sunk i io = 10 ma, v dd = 3.3 v 1.5 (1) v i io = 10 ma, v dd = 5 v 1.0 i io = 20 ma, v dd = 5 v 2.0 (1) notes: (1) data based on characterization results, not tested in production table 41: output driving current (high sink ports) symbol parameter conditions min max unit v ol output low level with four pins sunk i io = 10 ma, 1.1 (1) v docid14771 rev 13 63/ 99 electrical characteristics st m8s105xx symbol parameter conditions min max unit v dd = 3.3 v output low level with eight pins sunk i io = 10 ma, v dd = 5 v 0.9 output low level with four pins sunk i io = 20 ma, v dd = 5 v 1.6 (1) v oh output high level with four pins sourced i io = 10 ma, v dd = 3.3 v 1.9 (1) output high level with ei ght pins sourced i io = 10 ma, v dd = 5 v 3.8 output high level with four pins sourced i io = 20 ma, v dd = 5 v 2.9 (1) notes: (1) data based on characterization results, not tested in production 10.3.7 typical out put level curves the following figures show typical output level curves measured with output on a single pin. figure 27 : typ. vol @ vdd = 5 v (standard ports) 64/ 99 docid14771 rev 13 stm8s105xx electrical characteristics figure 28 : typ. vol @ vdd = 3.3 v (standard ports) figure 29 : typ. vol @ vdd = 5 v (true open drain ports) docid14771 rev 13 65/ 99 electrical characteristics st m8s105xx figure 30 : typ. vol @ vdd = 3.3 v (true open drain ports) figure 31 : typ. vol @ vdd = 5 v (high sink ports) 66/ 99 docid14771 rev 13 stm8s105xx electrical characteristics figure 32 : typ. vol @ vdd = 3.3 v (high sink ports) figure 33 : typ. vdd - voh @ vdd = 5 v (standard ports) figure 34 : typ. vd d - voh @ vdd = 3.3 v (standard ports) docid14771 rev 13 67/ 99 electrical characteristics st m8s105xx figure 35 : typ. vdd - voh @ vdd = 5 v (high sink ports) figure 36 : typ. vdd - voh @ vdd = 3.3 v (high sink ports) 10.3.8 reset pin characteristics subject to general operating conditions for v dd and t a unless otherwise specified. table 42: nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) nrst input low level voltage (1) - 0.3 - 0.3 x v dd v v ih(nrst) nrst input high level voltage (1) i ol =2 ma 0.7 x v dd - v dd + 0.3 v ol(nrst) nrst output low level voltage (1) - - 0.5 r pu(nrst) nrst pull -up resistor (2) 30 55 80 k t ifp(nrst) nrst input filtered pulse (3) - - 75 ns 68/ 99 docid14771 rev 13 stm8s105xx electrical character istics symbol parameter conditions min typ max unit t infp(nrst) nrst input not filtered pulse (3) 500 - - t op(nrst) nrst output pulse (3) 20 15 - - s notes: (1) data based on characterization results, not tested in production. (2) the r pu pull - up equivalent resistor is based on a resistive transistor (3) data guaranteed by design, not tested in production. figure 37 : typical nrst vil and vih vs vdd @ 4 temperatures figure 38 : typical nrst pull - up resistance vs vdd @ 4 temperatures docid14771 rev 13 69/ 99 electrical characteristics st m8s105xx figure 39 : typical nrst pull - up current vs vdd @ 4 temper atures the reset network shown in the following figure protects the device against parasitic resets. the user must ensure that the level on the nrst pin can go below v il(nrst) max. (see table 38: "i/o static characteristic s" ), otherwise the reset is not taken into account internally. for power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. if nrst signal is used to reset external circuitry, att ention must be taken to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. minimum recommended capacity is 100 nf. figure 40 : recommended reset pin protection 10.3.9 spi serial peripheral interface unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, f master frequency and v dd supply voltage con ditions. t master = 1/f master . refer to i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso). 70/ 99 docid14771 rev 13 stm8s105xx electrical characteristics table 43: spi characteristics symbol parameter conditions min max unit f sck 1 t c(sck) s pi clock frequency master mode 0 8 mhz slave mode 0 6 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf 25 ns t su(nss) (1) nss setup time slave mode 4 x t master ns t h(nss) (1) nss hold time slave mode 70 ns t w(sckh) (1) t w(sckl) (1) sck high and low time master mode t sck /2 - 15 t sck /2 + 15 ns t su(mi) (1) t su(si) (1) data input setup time master mode 5 ns data input setup time slave mode 5 ns t h(mi) (1) t h(si) (1) data i nput hold time master mode 7 ns data input hold time slave mode 10 ns t a(so) (1) (2) data output access time slave mode 3 x t master ns t dis(so) (1) (3) data output disable time slave mode 25 ns t v(so) (1) data output valid time slave mode (after enable edge) 73 ns t v(mo) (1) data output valid time master mode (after enable edge) 36 ns t h(so) (1) data output hold time slave mode (after enable edge) 28 ns t h(mo) (1) master mode (after enable edge ) 12 ns notes: (1) values based on design simulation and/or characterization results, and not tested in production. (2) min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. (3) min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi - z. docid14771 rev 13 71/ 99 electrical characteristics st m8s105xx figure 41 : spi timing diagram - slave mode and cpha = 0 figure 42 : spi timing diag ram - slave mode and cpha = 1(1) 1. measurement points are made at cmos levels: 0.3 v dd and 0.7 v dd . 72/ 99 docid14771 rev 13 stm8s105xx elec trical characteristics figure 43 : spi timing diagram - master mode(1) 1. measurement points are made at cmos levels: 0.3 v dd and 0.7 v dd . 10.3.10 i2c interface characteristics table 44: i2c characteristics symbol parameter standard mode i 2 c fast mode i 2 c (1) unit min (2) max (2) min (2) max (2) t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 s t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 (3) 0 (4) 900 (3) ns t r(sda) t r(scl) sda and scl rise time 1000 300 ns t f(sda) t f(scl) sda and scl fall time 300 300 ns t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 s t su(sto) stop condition setup time 4.0 0.6 s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 s docid14771 rev 13 73/ 99 electrical characteristics st m8s105xx symbol parameter standard mode i 2 c fast mode i 2 c (1) unit min (2) max (2) min (2) max (2) c b capacitive load for each bus line 400 400 pf notes: (1) f master , must be at least 8 mhz to achieve max fast i 2 c speed (400khz). (2) data based on standard i 2 c protocol requirement, not tested in production. (3) the maximum hold time of the start condition has only to be met if the interface does not stret ch the low time. (4) the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the falling edge of scl. figure 44 : typical application with i2c bus and timin g diagram (1) 1. measurement points are made at cmos levels: 0.3 x v dd and 0.7 x v dd 10.3.11 10- bit adc characteristics subject to general operating conditions for v dda , f master , and t a unless otherwise specifie d. table 45: adc characteristics symbol parameter conditions min typ max unit f adc adc clock frequency v dda =2.95 to 5.5 v 1.0 4.0 mhz v dda =4.5 to 5.5 v 1.0 6.0 v dda analog supply 3.0 5.5 v v ref+ positive reference voltage 2.75 (1) v dda v v ref - negative reference voltage vssa 0.5 v 74/ 99 docid14771 rev 13 stm8s105xx electrical characteristics symbol parameter conditions min typ max unit (1) v ain conversion voltage range (2) vssa vdda v devices with external v ref + /v ref - pins v ref - v ref+ v c adc internal sample and hold capacitor 3.0 pf t s (2) sampling time f adc = 4 mhz 0.75 s f adc = 6 mhz 0.5 t stab wakeup time from standby 7.0 s t conv total conversion time (including sampling time, 10 - bit resolution) f adc = 4 mhz 3.5 s f adc = 6 mhz 2.33 s 14 1/f adc notes: (1) data guaranteed by design, not tested in production.. (2) during the sample time the input capacitance c ain (3 pf max) can be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within t s. after the end of the sample time t s , changes of the analog input voltage have no effect on the c onversion result. values for the sample clock t s depend on programming. table 46: adc accuracy with rain < 10 k , vdda= 5 v symbol parameter conditions typ max (1) unit |e t | total unadjusted error (2) f adc = 2 mhz 1.0 2.5 lsb f adc = 4 mhz 1.4 3.0 f adc = 6 mhz 1.6 3.5 |e o | offset error (2) f adc = 2 mhz 0.6 2.0 f adc = 4 mhz 1.1 2.5 f adc = 6 mhz 1.2 2.5 |e g | gain error (2) f adc = 2 mhz 0.2 2.0 f adc = 4 mhz 0.6 2.5 f adc = 6 mhz 0.8 2.5 |e d | differential linearity error (2) f adc = 2 mhz 0.7 1.5 f adc = 4 mhz 0.7 1.5 f adc = 6 mhz 0.8 1.5 |e l | integral linearity error (2) f adc = 2 mhz 0.6 1.5 f adc = 4 mhz 0.6 1.5 f adc = 6 mhz 0.6 1.5 notes: (1) data based on characterization results, not tested in pro duction. (2) adc accuracy vs. negative injection current: injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. docid14771 rev 13 75/ 99 electrical characteristics st m8s105xx it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in the i/o port pin characteristics section does not affe ct the adc accuracy. 7 d e o h $ ' & d f f x u d f \ z l w k 5 $ , 1 n 5 $ , 1 9 ' ' $ 9 symbol parameter conditions typ max (1) unit |e t | total unadjusted error (2) f adc = 2 mhz 1.1 2.0 lsb f adc = 4 mhz 1.6 2.5 |e o | offset error (2) f adc = 2 mhz 0.7 1.5 f adc = 4 mhz 1.3 2.0 |e g | gain error (2) f adc = 2 mhz 0.2 1.5 f adc = 4 mhz 0.5 2.0 |e d | differential linearity error (2) f adc = 2 mhz 0.7 1.0 f adc = 4 mhz 0.7 1.0 |e l | integral linearity error (2) f adc = 2 mhz 0.6 1.5 f adc = 4 mhz 0.6 1.5 notes: (1) data based on characterization results, not tested in production. (2) adc accuracy vs. negative injection current: injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of th e conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 13.3.6: "i/o port pin characteristics" does not affect the adc accuracy. figure 45 : adc accuracy characteristics 1. example of an actual transfer curve. 2. the ideal transf er curve 76/ 99 docid14771 rev 13 stm8s105xx electrical characteristics 3. end point correlation line e t = total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o = offset error: deviation between the first actual transition and the first ideal one. e g = gain error: deviation be tween the last ideal transition and the last actual one. e d = differential linearity error: maximum deviation between actual steps and the ideal one. e l = integral linearity error: maximum deviation between any actual transition and the end point correla tion line. figure 46 : typical application with adc 10.3.12 emc characteristics susceptibility tests are performed on a sample basis during product characterization. 10.3.12.1 functional ems (electrom agnetic susceptibility) while executing a simple application (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic events until a failure occurs (indicate d by the leds). ? fesd: functional electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 61000 - 4 - 2 standard. ? ftb: a burst of fast transient voltage (posit ive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test conforms to iec 61000 - 4 - 4 standard. a device reset allows normal operations to be resumed. test results are given in table below based on the ems levels and classes defined in application note an1709 (emc design guide for st microcontrollers). 10.3.12.2 designing hardened software to avoid noise problems emc characteriz ation and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions su ch as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) docid14771 rev 13 77/ 99 electrical characteristics st m8s105xx prequalification trials most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the nrs t pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable erro rs occurring. see application note an1015 (software techniques for improving microcontroller emc performance). table 48: ems data symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, t a = 25 c, f master = 16 mhz (hsi clock), conforming to iec 61000 -4 - 2 v dd = 5 v, t a = 25 c, f master = 16 mhz, conforming to iec 1000 -4 -2 2/b (1) v eftb fast transient voltage burst limits t o be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, t a = 25 c ,f master = 16 mhz (hsi clock),conforming to iec 61000 -4 - 4 v dd = 5 v, t a = 25 c ,f master = 16 mhz,conforming to iec 1000 - 4 -4 4/a (1) notes: (1) data obtained with hsi clock configuration, after applying hw recommendations described in an2860 (emc guidelines for stm8s microcontrollers). 10.3.12.3 electromagnetic interference (emi) emission tests conform to the iec61967 - 2 standard for test software, board layout and pin loading. table 49: emi data symbol parameter conditions unit general conditions monitored frequency band max f hse /f cpu (1) 8 mhz/ 8 mhz 8 mhz/ 16 mhz s emi peak level v dd = 5 v, t a = +25 c, lqfp48 package conforming to iec61967 - 2 0.1 mhz to 30 mhz 13 14 dbv 30 mhz to 130 mhz 23 19 130 mhz to 1 ghz - 4.0 - 4.0 sae emi leve l 2.0 1.5 ? notes: (1) data based on characterization results, not tested in production. 78/ 99 docid14771 rev 13 stm8s105xx electrical characteristics 10.3.12.4 absolute maximum ratings (electrical sensitivity) based on two different tests (es d and lu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. for more details, refer to the application note an1181. 10.3.12.5 electrostatic discharge (esd) electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). this test conforms to the jesd22 - a114a/a115a standard. for more details, refer to the application note an1181. table 50: esd absolute maximum ratings symbol ratings conditions class maximum value (1) unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25c, conforming to jesd22 - a114 a 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a =+25c, conforming to jesd22 - c101 iv 1000 v notes: (1 ) data based on characterization results, not tested in production 10.3.12.6 static latch -up two complementary static tests are required on 10 parts to assess the latch - up performance: ? a supply overvoltage (applied to ea ch power supply pin) ? a current injection (applied to each input, output and configurable i/o pin) is performed on each sample. this test conforms to the eia/jesd 78 ic latch - up standard. for more details, refer to the application note an1181. table 51: electrical sensitivities symbol parameter conditions class (1) lu static latch - up class t a = +25 c a t a = +85 c a t a = +125 c a notes: (1) class description: a class is a stmicroelectronics internal specification. all limits are higher than jedec specifications, that means when a device belongs to class a it exceeds jedec standard. b class strictly covers all the jedec criteria (international standard). docid14771 rev 13 79/ 99 package information st m8s105xx 11 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark. 11.1 48- pin lqfp package mechanical data figure 47 : 48- pin low profile quad flat package (7 x 7) table 52: 48 - pin low profile quad flat packa ge mechanical data dim. mm inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.008 7 0.0106 c 0.090 0.200 0.0035 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 5.500 0.2165 e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2 756 0.2835 e3 5.500 0.2165 e 0.500 0.0197 80/ 99 docid14771 rev 13 stm8s105xx package information dim. mm inches (1) min typ max min typ max l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 0 3.5 7.0 0 3.5 7.0 ccc 0.080 0.0031 notes: (1) values in inches are converted from mm and rounde d to 4 decimal digits 11.2 44- pin lqfp package mechanical data figure 48 : 44- pin low profile quad flat package table 53: 44 - pin low profile quad flat package mechanical data dim. mm inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 0.200 0.0035 0.0079 d 11.800 12.000 12.200 0.4646 0.4724 0.4803 d1 9.800 10.000 10.200 0.3858 0.3937 0.4016 d3 8.000 0.3150 e 11.800 12.000 12.200 0.4646 0.4724 0.4803 e1 9.800 10.000 10.200 0.3858 0.3937 0.4016 docid14771 rev 13 81/ 99 package information st m8s105xx dim. mm inches (1) min typ max min typ max e3 8.000 0.3150 e 0.800 0.0315 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 0.0 3.5 7.0 0.0 3.5 7.0 ccc 0.100 0.0039 notes: (1) values in inches are converted from mm and rounded to 4 decimal digits 11.3 32- pin lqfp package mechanical data figure 49 : 32- pin low profile quad flat package (7 x 7) table 54: 32 - pin low profile quad flat package mech anical data dim. mm inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0 .0118 0.0146 0.0177 c 0.090 0.200 0.0035 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 5.600 0.2205 82/ 99 docid14771 rev 13 stm8s105xx package information dim. mm inches (1) min typ max min typ max e 8.800 9.000 9.200 0.3465 0.3543 0. 3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 5.600 0.2205 e 0.800 0.0315 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 0 3.5 7.0 0 3.5 7.0 ccc 0.10 0 0.0039 notes: (1) values in inches are converted from mm and rounded to 4 decimal digits docid14771 rev 13 83/ 99 package information st m8s105xx 11.4 32- lead ufqfpn package mechanical data figure 50 : 32- lead, ultra - thin , fine pitch quad flat no - lead package (5 x 5) 1. drawing is not to scale. 2. all leads/pads should be soldered to the pcb to improve the lead/pad solder joint life. 3. there is an exposed die pad on the underside of the ufqfpn package. it is recommended to conn ect and solder this backside pad to pcb ground. 4. dimensions are in millimeters. table 55: 32 - lead ultra - thin fine pitch quad flat no - lead package mechanical data dim. mm inches (1) min typ max min typ max a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 0 0.020 0.050 0.0008 0.0020 a3 0.200 0.0079 b 0.180 0.250 0.300 0.0071 0.0098 0.0118 d 4.900 5.000 5.100 0.1909 0.1969 0.2028 d2 3.200 3.450 3.700 0.1260 0.1457 e 4.900 5.000 5.100 0.1909 0.1969 0.2028 84/ 99 docid14771 rev 13 stm8s105xx package inf ormation dim. mm inches (1) min typ max min typ max e2 3.200 3 .450 3.700 0.1260 0.1358 0.1457 e 0.500 0.0197 l 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd 0.080 0.0031 notes: (1) values in inches are converted from mm and rounded to 4 decimal digits. 11.5 sdip32 package mechanical data figure 51 : 32- lead shrink plastic dip (400 ml) package docid14771 rev 13 85/ 99 package information st m8s105xx table 56: 32 - lead shrink plastic dip (400 ml) package mechanical data dim. mm inches (1) min t yp max min typ max a 3.556 3.759 5.080 0.1400 0.1480 0.2000 a1 0.508 0.0200 a2 3.048 3.556 4.572 0.1200 0.1400 0.1800 b 0.356 0.457 0.584 0.0140 0.0180 0.0230 b1 0.762 1.016 1.397 0.0300 0.0400 0.0550 c 0.203 0.254 0.356 0.0079 0.0100 0.0140 d 27.430 27.940 28.450 1.0799 1.1000 1.1201 e 9.906 10.410 11.050 0.3900 0.4098 0.4350 e1 7.620 8.890 9.398 0.3000 0.3500 0.3700 e 1.778 0.0700 ea 10.160 0.4000 eb 12.700 0.5000 l 2.540 3.048 3.810 0.1000 0.1200 0.1500 notes: (1) values in inches are converted from mm and rounded to 4 decimal digits 86/ 99 docid14771 rev 13 stm8s105xx thermal characteristics 12 thermal characteristics the maximum chip junction temperature (t jmax ) must never exceed the values given in section 7.10: "tim1 - 16- bit advanced control timer" the maximum chip - junction temperature, t jmax , in degrees celsius, may be calculated using the following equation: t jmax = t amax + (p dmax x ja ) where: x t amax is the maximum ambient temperature in c x ja is the package junction - to - ambient thermal resistance in c/w x p dmax is the sum of p intmax and p i/omax (p dmax = p intmax + p i/omax ) x p intmax is the product of i dd andv dd , expressed in wat ts. this is the maximum chip internal power. x p i/omax represents the maximum power dissipation on output pinswhere:p i/omax = (v ol *i ol ) + ((v dd - v oh) *i oh ), taking into account the actual v ol /i ol and v oh /i oh of the i/os at low and high level in the applicat ion. table 57: thermal characteristics (1) symbol parameter value unit ja thermal resistance junction - ambient lqfp 48 - 7 x 7 mm 57 c/w ja thermal resistance junction - ambient lqfp 44 - 10 x 10 mm 54 c/w ja thermal resistance junction - ambient lqfp 32 - 7 x 7 mm 60 c/w ja thermal resistance junction - ambient ufqfpn 32 - 5 x 5 mm 38 c/w ja thermal resistance junction - ambient sdip 32 - 400 mils 60 c/w 1. thermal resistances are based on jedec jesd51 - 2 with 4 - layer pcb in a natural convection environment. 12.1 reference document jesd51 - 2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. 12.2 selecting the produc t temperature range when ordering the microcontroller, the temperature range is specified in the order code. the following example shows how to calculate the temperature range needed for a give n application. assuming the following application conditions: x maximum ambient temperature t amax = 82 c (measured according to jesd51 - 2) x i ddmax = 15 ma, v dd = 5.5 v docid14771 rev 13 87/ 99 thermal characteristics st m8s105xx ? maximum 8 standard i/os used at the same time in output at low level with i ol = 10 ma, v ol = 2 v ? maximum 4 high sink i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.5 v ? maximum 2 true open drain i/os used at the same time in output at low level with i ol = 20 ma, v ol = 2 v p intmax = 15 ma x 5.5 v = 82.5 mw p iomax = (10 ma x 2 v x 8 )+(20 ma x 2 v x 2)+(20 ma x 1.5 v x 4) = 360 mw this gives: p intmax = 82.5 mw and p iomax 360 mw: p dmax = 82.5 mw + 360 mw thus: p dmax = 443 mw t jmax i r u / 4 ) 3 f d q e h f d o f x o d w h g d v i r o o r z v x v l q j w k h w k h u p d o u h v l v w d q f h , ja : t jmax = 82 c + (60 c/w x 443 mw) = 82c + 27c = 109 c this is within the range of the suffix 3 version parts ( - 40 < t j < 131 c). in this case, parts must be ordered at least with the temperature range suffix 3. 88/ 99 docid14771 rev 13 stm8s105xx ordering information 13 ordering information figure 52 : stm8s105xx access line ordering information scheme 1. for a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device , please go to www.st.com or contact the st sales office nearest to you. docid14771 rev 13 89/ 99 stm8s105 fastrom microcontroller option list st m8s105xx 14 stm8s105 fastrom microcontroller option list (last update: september 2010) customer ......................... ...................................................................................... address ............................................................................................................... contact ....................................... ........................................................................ phone no. ............................................................................................................... reference fastrom code (1) ............................................................................................................... notes: (1) fastrom code name is assigned by stmicroelectronics. preferable format for programing code is .hex (.s19 is accepted) if data e eprom programing is required, a separate file must be sent with the requested data. see the option byte section in the datasheet for authorized option byte combinations and a detailed explanation. device type/memory size/package (check only one opti on) fastrom device 16 kbyte 32 kbyte lqfp32 [ ] stm8s105k4 [ ] stm8s105k6 lqfp44 [ ] stm8s105s4 [ ] stm8s105s6 lqfp48 [ ] stm8s105c4 [ ] stm8s105c6 conditioning (check only one option) [ ] tape & reel or [ ] tray special marking (check only one opti on) [ ] no [ ] yes authorized characters are letters, digits, '.', ' - ', '/' and spaces only. maximum character counts are: lqfp32: 2 lines of 7 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _" lqfp44: 2 lines of 7 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _" lqfp48: 2 lines of 8 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _" temperature range [ ] - 40c to +85c or [ ] - 40c to +125c 90/ 99 docid14771 rev 13 stm8s105xx stm8s105 fastrom microcontroller option list padding value for unused program memory (check only one option) [ ] 0xff fixed value [ ] 0x83 trap ins truction opcode [ ] 0x75 illegal opcode (causes a reset when executed) opt0 memory readout protection (check only one option) [ ] disable or [ ] enable opt1 user boot code area (ubc) 0x(_ _) fill in the hexadecimal value, referring to the datasheet a nd the binary format below. ubc, bit0 [ ] 0: reset [ ] 1: set ubc bit1 [ ] 0: reset [ ] 1: set ubc bit2 [ ] 0: reset [ ] 1: set ubc bit3 [ ] 0: reset [ ] 1: set ubc bit4 [ ] 0: reset [ ] 1: set ubc bit5 [ ] 0: reset [ ] 1: set opt2 alte rnate function remapping afr0 (check only one option) [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description. [ ] 1: port d3 alternate function = adc_etr afr1 (check only one option) [ ] 0: remapping option i nactive. default alternate functions used. refer to pinout description. [ ] 1: port a3 alternate function = tim3_ch1, port d2 alternate function = tim2_ch3. afr2 (check only one option) [ ] 0: remapping option inactive. default alternate functions use d. refer to pinout description. [ ] 1: port d0 alternate function = clk_cco. if both afr2 and afr3 are activated, afr2 option has priority over afr3. afr3 (check only one option) [ ] 0: remapping option inactive. default alternate functions used . refer to pinout description. [ ] 1: port d0 alternate function = tim1_bkin. docid14771 rev 13 91/ 99 st m8s105 fastrom microcontroller option list st m8s105xx afr4 (check only one option) [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description. [ ] 1: port d7 alternate function = tim1_ch4. afr5 (check only one option) [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description. [ ] 1: port b3 alternate function = tim1_etr, port b2 alternate function = tim1_ncc3, port b1 alternate function = tim1_ch2n, port b0 alternate function = tim1_ch1n. afr6 (check only one option) [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description [ ] 1: port b5 alternate function = i2c_sda, port b4 alternate function = i2c_scl. afr7 (check only one option) [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description. [ ] 1: port d4 alternate function = beep. opt3 watchdog wwdg_halt (check only one option) [ ] 0: no reset generated on hal t if wwdg active. [ ] 1: reset generated on halt if wwdg active. wwdg_hw (check only one option) [ ] 0: wwdg activated by software. [ ] 1: wwdg activated by hardware. iwdg_hw (check only one option) [ ] 0: iwdg activated by software. [ ] 1: iwdg activated by hardware. lsi_en (check only one option) [ ] 0: lsi clock is not available as cpu clock source. [ ] 1: lsi clock is available as cpu clock source. hsitrim (check only one option) [ ] 0: 3 - bit trimming supported in clk_hsitrimr regist er. [ ] 1: 4 - bit trimming supported in clk_hsitrimr register. opt4 wakeup prsc (check only one option) [ ] for 16 mhz to 128 khz prescaler. [ ] for 8 mhz to 128 khz prescaler. [ ] for 4 mhz to 128 khz prescaler. ckawusel (check only one option) [ ] 0: lsi clock source selected for awu. [ ] 1: hse clock with prescaler selected as clock source for awu. extclk (check only one option) [ ] 0: external crystal connected to oscin/oscout. [ ] 1: external clock signal on oscin. opt5 crystal osci llator stabilization hsecnt (check only one option) [ ] 2048 hse cycles [ ] 128 hse cycles [ ] 8 hse cycles [ ] 0.5 hse cycles 92/ 99 docid14771 rev 13 stm8s105xx stm8s105 fastrom microcontroller option list opt6 is reserved opt7 is reserved optbl bootloader option byte (check only one option) refer to the um0560 (stm8l/s bootloade r manual) for more details. [ ] disable (00h) [ ] enable (55h) comments: ........................................................................................... supply operating range in the application ............................................. .............................................. notes: ........................................................................................... date: ........................................................................................... signature : ........................................................................................... docid14771 rev 13 93/ 99 stm8 development tools st m8s105xx 15 stm8 development tools development tools for the stm8 microcontrollers include the full - featured stice emulati on system supported by a complete software tool package including c compiler, assembler and integrated development environment with high - level language debugger. in addition, the stm8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low - cost in - circuit debugger/programmer. 15.1 emulation and in - circuit debugging tools the stice emulation system offers a complete range of emulation and in - circuit debuggi ng features on a platform that is designed for versatility and cost - effectiveness. in addition, stm8 application development is supported by a low - cost in - circuit debugger/programmer. the stice is the fourth generation of full featured emulators from stmi croelectronics. it offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. in addition, stice offers in - circuit debugging and programming of stm8 microcontrollers via the stm8 single wire interface module (swim), which allows non - intrusive debugging of an application while it runs on the target microcontroller. for improved cost effectiveness, stice is based on a modular des ign that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future st microcontrollers. stice key features ? occurrence and time profiling and code coverage (new feature s) ? advanced breakpoints with up to 4 levels of conditions ? data breakpoints ? program and data trace recording up to 128 kb records ? read/write on the fly of memory during emulation ? in - circuit debugging/programming via swim protocol ? 8 - bit probe analyzer ? 1 input and 2 output triggers ? power supply follower managing application voltages between 1.62 to 5.5 v ? modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements ? supported by fr ee software tools that include integrated development environment (ide), programming software interface and assembler for stm8. 15.2 software tools stm8 development tools are supported by a complete, free software packa ge from stmicroelectronics that includes st visual develop (stvd) ide and the st visual programmer (stvp) software interface. stvd provides seamless integration of the cosmic and raisonance c compilers for stm8, which are available in a free version that o utputs up to 16 kbytes of code. 15.2.1 stm8 toolset stm8 toolset with stvd integrated development environment and stvp programming software is available for free download at www.st.com/mcu. this package includes: 94/ 99 docid14771 rev 13 stm8s105xx stm8 development tools st visual develop ? full - featured integrated development environment from st, featuring ? seamless integration of c and asm toolsets ? full - featured debugger ? project management ? syntax highlighting editor ? integrated programming interface ? support of advanced emulat ion features for stice such as code profiling and coverage st visual programmer (stvp) ? easy - to - use, unlimited graphical interface allowing read, write and verify of your stm8 microcontroller?s flash program memory, data eeprom and option bytes. stvp als o offers project mode for saving programming configurations and automating programming sequences. 15.2.2 c and assembly toolchains control of c and assembly toolchains is seamlessly integrated into the stvd integra ted development environment, making it possible to configure and control the building of your application directly from an easy - to - use graphical interface. available toolchains include: ? cosmic c compiler for stm8 ? available in a free version that output s up to 16 kbytes of code. for more information, see www.cosmic - software.com. ? raisonance c compiler for stm8 ? available in a free version that outputs up to 16 kbytes of code. for more information, see www.raisonance.com. ? stm8 assembler linker ? free as sembly toolchain included in the stvd toolset, which allows you to assemble and link your application source code. 15.3 programming tools during the development cycle, stice provides in - circuit programming of the stm 8 flash microcontroller on your application board via the swim protocol. additional tools are to include a low - cost in - circuit programmer as well as st socket boards, which provide dedicated programming platforms with sockets for programming your stm8. fo r production environments, programmers will include a complete range of gang and automated programming solutions from third - party tool developers already supplying programmers for the stm8 family. docid14771 rev 13 95/ 99 revision history st m8s105xx 16 revision history table 58: document revision history date revision changes 05- jun - 2008 1 initial release. 23- jun - 2008 2 corrected number of high sink outputs to 9 in i/os on section 3: "features" . updated part numbers in table 2: "stm8s105xx access line features" . 12- aug - 2008 3 updated part numbers in table 2: "stm8s105xx access line features" . usart renamed uart1, linuart renamed uart2. added table 7: pin -to - pin comparison of pin 7 to 12 in 32- pin access line devices. 17- sep - 2008 4 removed stm8s102xx and stm8s104xx root part numbers corresponding to devices without data eeprom. updated stm8s103 pinout in section 5.2 on page 29. added low and medium density flash memory categories. added note 1 in table 17: "current characteristics" . updated table 12: "option bytes " . 05- feb- 2009 5 updated stm8s103 pinout in section 5.2 on page 29 updated nu mber of high sink i/os in pinout. tssop20 pinout modified (pd4 moved to pin 1 etc.) added wfqfn20 package updated section 11: "option bytes" . added section 4: "introduction" . 27- feb- 2009 6 removed stm8s103x products (separate stm8s103 datasheet created) updated section 4: "introduction" . 12- may - 2009 7 added sdip32 silhouette and package to section 3: "features" and section 14.5: "sdip32 package mechanical data" ; updated section 8: "pinout and pin description" . updated v dd range (2.95 v to 5.5 v) on section 3: "features" . ame nded name of package vqfpn32 added table 5 on page 22 . updated section 7.8: "auto wakeup counter" . updated pins 25, 30, and 31 in section 8: "pinout and pin description" . removed table 7: p in -to - pin comparison of pin 7 to 12 in 32- pin access line devices. added table 14: "description of alternate function remapping bits [7:0] of opt2" . section 4: "introduction" : updated vcap s pecifications; updated table 15, table 18, table 20, table 21, table 22, table 23, table 24, table 25, table 26, table 27, table 29, table 35, and table 42; added current consumption curves ; removed figure 20: typical hse frequency vs fcpu @ 4 temperature s; updated figure 13, figure 14, figure 15, figure 16 and figure 17 ; modified hsi accuracy in table 33 ; added figure 44 ; modified fsck, tv(so) and tv(mo) in table 42 ; updated figures and tables of high speed internal rc oscillator (hsi) ; replaced figu re 23, figure 24, figure 26, and figure 39 . section 14: "package information" : updated table 57: "thermal 96/ 99 docid14771 rev 13 stm8s105xx revision history date revision changes characteristics(1)" and removed table 57: junction temperature range. updated figure 52: "stm8s105xx access line ordering information scheme" . 10- jun - 2009 8 document status changed from ?preliminary data? to ?datasheet?. standardized name of the vfqfpn package. removed ?wpu? from i2c pins in section 8: "pinout and pin description" 21- apr - 2010 9 added ufqfpn32 package silhouette to the title page. section 3: "features" : added unique id. section 7.4: "flash program and data eeprom memory" : updated bit positions for tim2 and tim3. section 7.9: "beeper" : added information about availability of the beeper output port through option bit afr7. section 7.13: "analog -to - digital converter (adc1)" : added a note concerning additional ain12 analog input. section 8.1: "stm8s105 pinouts and pin description" : added ufqfpn32 package details; updated default alternate function of pb2/ain2[tim1_ch3n] pin in the "pin description for stm8s105 microcontrollers" table. section 11: "option bytes" : added description of stm8l bootloader option bytes to the option byte description tabl e. added section 4: "introduction" section 7.10: "tim1 - 16- bit advanced control timer" : added introductory text; removed low power dissipation condition for t a , replaced "c ext " by "vcap", a nd added esr and esl data in table "general operating conditions". section 13.3.2.4: "total current consumption in halt mode" : replaced max value of i dd(h) at 85 c from 20 a to 25 a for the condition "flash in powerdown mode, hsi clock after wakeup in the table "total current consumption in halt mode at v dd = 5 v. section 13.3.2.5: "low power mode wakeup times" : added first condition (0 to 16 mhz) for the t wu(wfi) parameter in the table "w akeup times". section 13.3.4: "internal clock sources and timing characteristics" : in the table "hsi oscillator characteristics", replaced min and max values of "acc hsi factory calibrated parameter" and removed footnote 4 c oncerning further characterization of results. section 13.3.12.1: "functional ems (electromagnetic susceptibility)" : iec 1000 replaced with iec 61000. section 13.3.12.2: "designing hardened s oftware to avoid noise problems" : iec 1000 replaced with iec 61000. section 13.3.12.3: "electromagnetic interference (emi)" : sae j 1752/3 replaced with iec61967 - 2. section 7.7: "watchdog tim ers" : replaced the thermal resistance junction ambient temperature of lqfp32 7x7 mm from 59 c to 60 c in the thermal characteristics table. added section 6: "block diagram" . added section 17: "stm8s105 fastrom microcontroller option list" . 21- sep - 2010 10 table 5: "legend/abbreviations for pinout tables " : updated "reset state"; removed "hs", (t), and "[ ]". table 6: "pin d escription for stm8s105 microcontrollers" : added footnotes to the pf4 and pd1 pins. table 8: "i/o port hardware register map" : changed reset status of px_idr from 0x00 to 0xxx. table 9: "gen eral hardware register map" : standardized all address and reset state values; updated the reset state values of the rst_sr, clk_swcr, clk_hsitrimr, clk_swimccr, iwdg_kr, uart2_dr, and adc_drx docid14771 rev 13 97/ 99 revision history st m8s105xx date revision changes registers; replaced reserved address "0x00 5248" with the uart2 _cr5. figure 40: "recommended reset pin protection" : replaced 0.01 f with 0.1 f updated figure 44: "typical application with i2c bus and timing diagram (1)" . updated footnote 1 in table 46: adc accuracy with rain < 10 k , vdda= 5v and table 47: adc accuracy with rain < 10 k rain, vdda=3.3v . section 17: "stm8s105 fastrom microcontroller optio n list" : removed bits 6 and 7 from opt1 user boot code area (ubc); added "disable" to 00h and "enable" to 55h of optbl bootloader option byte. vfqfpn package mechanical datas : replaced note 1 and added note 2. 04- apr - 2012 11 removed vfqfpn32 package. modified section 5: "description" . remove weak pull - up input for pe1 and pe2 in table 6: "pin description for stm8s105 microcontrollers" updated table 11: "in terrupt mapping" for tim2 and tim4. updated notes related to v cap in table 19: "general operating conditions" . added values of t r /t f for 50 pf load capacitance, and updated note in table 38: "i/o static characteristics" . updated typical and maximum values of r pu in table 38: "i/o static characteristics" and table 42: "nrst pin characteristics" . changed sck input to sck output in section 13.3.9: "spi serial peripheral interface" $ g g h g , ja for ufqfpn32 and sdip32 in table 57: "thermal characteristics(1)" , and updated section 7.9: "be eper" 28- jun - 2012 12 added ufqfpn package thickness in figure 52: "stm8s105xx access line ordering information scheme" . 7 - feb- 2014 13 uart2_ck mapped to correct pin (pin 24) in figure 4: "lqfp 44 - pin pinout" . reserved area updated in table 12: "option bytes " . package information updated in table 55: "32 - lead ultra - thin fine pitch quad flat no - lead package mechanical data " . 98/ 99 docid14771 rev 13 stm8s105xx disclaimer 17 disclaimer please read carefully information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, modifications o r improvements, to this document, and the products and services described herein at any time , without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st assumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellec tual property rights is granted under this document. if any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringe ment of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety require ments; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has b een informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualif ied are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoever, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersed es and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of co mpanies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - unite d states of america www.st.com docid14771 rev 13 99/ 99 |
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